An open API service providing repository metadata for many open source software ecosystems.

Topic: "rtl-design"

4xmen/Web-Package-RTL

⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

Language: HTML - Size: 19.4 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 664 - Forks: 205

pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language: Verilog - Size: 43 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 308 - Forks: 92

4xmen/x-mega-menu

x mega menu is repsonsive mega menu based on vannilajs

Language: JavaScript - Size: 1010 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 184 - Forks: 43

pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Language: SystemVerilog - Size: 107 MB - Last synced at: 13 days ago - Pushed at: 14 days ago - Stars: 178 - Forks: 86

4xmen/x-tree-select

Tree Select jQuery plugin

Language: JavaScript - Size: 361 KB - Last synced at: about 8 hours ago - Pushed at: 6 days ago - Stars: 105 - Forks: 26

mirseo/JSilicon

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

Language: SystemVerilog - Size: 1.23 MB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 94 - Forks: 9

4xmen/rvnm

Responsive vertical navigation menu

Language: CSS - Size: 11.6 MB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 65 - Forks: 8

snbk001/100DaysofRTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

Language: SystemVerilog - Size: 120 KB - Last synced at: 6 months ago - Pushed at: about 3 years ago - Stars: 34 - Forks: 3

AUCOHL/RTL-Repo

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

Language: Python - Size: 202 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 21 - Forks: 2

synogate/gatery

Gatery, a library for circuit design.

Language: C++ - Size: 8.29 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 17 - Forks: 5

esynr3z/pip-hdl

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

Language: Python - Size: 55.7 KB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 8 - Forks: 0

Choaib-ELMADI/getting-started-with-systemverilog

Getting started with SystemVerilog: Hardware Description Language for design and verification.

Language: SystemVerilog - Size: 1.26 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 7 - Forks: 1

maazm007/100Daysof_RTL

The Repository contains the code of various Digital Circuits

Language: Verilog - Size: 20.6 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 1

CIE-PESU/CIE_RISCV_Project

RISC-V K-Nearest Neighbors Accelerator for Image Recognition on FPGA

Language: Assembly - Size: 21.9 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 4 - Forks: 1

synogate/gatery_template

Template project for using gatery

Language: C++ - Size: 22.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 4 - Forks: 1

Luca-Dalmasso/DLX

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

Language: Verilog - Size: 16.3 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 1

Sanjaydulipudi/PIPELINED_ADDER

8-input pipelined adder tree in Verilog with simulation & synthesis results.

Language: Verilog - Size: 497 KB - Last synced at: 4 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 0

SKpro-glitch/Parallel_Multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 2 - Forks: 0

MohamedHussein27/RISC-V-Single-Cycle-Implementation

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.

Language: Verilog - Size: 11.4 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

williaml33moore/bathtub Fork of everactive/bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

Language: SystemVerilog - Size: 7.61 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

Abdelrahman1810/SPI_Slave_with_Single_Port_RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

Language: Verilog - Size: 401 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

alirezajaberirad/Object-Oriented-Modeling-of-Electronic-Circuits

This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022

Language: C++ - Size: 7.06 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

sidhantp1906/AMBA4-APB

Advanced Pheripheral Bus design using verilog HDL

Language: Verilog - Size: 348 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

gabrielganzer/RTSNoC-Sniffer

Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.

Language: C++ - Size: 29.3 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

kirthana1181/AXI4-Lite-based_Data-Sorter

In this repository, an AXI4-Lite Protocol Slave Peripheral Transaction has been coded that can receive data packets, validate them based on sorting condition valid or invalid storage. The design of storages is a simple FIFO-like sorting.

Language: JavaScript - Size: 811 KB - Last synced at: 3 days ago - Pushed at: 7 days ago - Stars: 1 - Forks: 0

itworks99/vtx1

Balanced ternary logic SoC with CPU, memory controllers, and complete synthesis flow for silicon fabrication

Language: Verilog - Size: 14.8 MB - Last synced at: 7 days ago - Pushed at: 10 days ago - Stars: 1 - Forks: 1

iDsiddy/VHDL-Verilog-Projects

Collection of RTL design projects implemented in VHDL and Verilog, including controllers, FSMs, and FPGA-ready modules.

Language: VHDL - Size: 2.06 MB - Last synced at: 15 days ago - Pushed at: 18 days ago - Stars: 1 - Forks: 0

adityark2603/The-RTL-Files

A collection of systemverilog designs implemented on AMD Vivado tool

Language: SystemVerilog - Size: 7.62 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

dighrasker/MultiCore_L2_Cache

A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.

Language: SystemVerilog - Size: 58.6 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

Ammar-Bin-Amir/I2C

RTL Design of Inter-Integrated Circuit

Language: Verilog - Size: 538 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

Farbod-Siahkali/Digital-Logical-Designs-Projects

Digital Logical Designs Course Projects

Language: Verilog - Size: 4.66 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Luca-Dalmasso/RISCV_LBIST Fork of alessandrolandra/RISCV_LBIST

Design of a BIST module for RISC-V fault testing

Size: 60.2 MB - Last synced at: almost 3 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

Luca-Dalmasso/Max-Pooling_VHDL

HLSM with memory design for max pooling algorithm.

Language: VHDL - Size: 1.71 MB - Last synced at: almost 3 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

SuggarGrandma420/Router-1x3

🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.

Language: JavaScript - Size: 16.4 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

ravez24/verilog-c2w

🎛️ Convert Verilog code to C for efficient simulation and synthesis, streamlining design workflows and enhancing hardware development processes.

Size: 1.29 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 2

Gonsukey/verilog-uhj

🛠️ Streamline your hardware design with Verilog-UHJ, an efficient framework for creating and managing digital circuit simulations.

Size: 1.29 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

ateo44/vhdl-5sv

🔧 Enhance your VHDL designs with vhdl-5sv, a streamlined tool for efficient simulation and verification of VHDL code.

Size: 1.29 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

Analysissitusgagarin418/vhdl-4hn

⚙️ Transform VHDL design processes with vhdl-4hn, a lightweight library that streamlines hardware description and enhances code readability.

Size: 1.3 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

linearalgebragenusblatta897/vhdl-gkr

🔍 Explore VHDL implementations of GKR protocols for efficient proof systems, enhancing performance in verification and computational tasks.

Size: 1.3 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

Opvenom1001/vhdl-yr7

🚀 Explore VHDL designs for Year 7 projects, enhancing learning in digital logic through hands-on examples and simulations.

Size: 1.29 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

MCasoni-reborn/vhdl-4my

⚙️ Streamline your VHDL workflows with vhdl-4my, a tool designed for efficient design, testing, and visualization of VHDL projects.

Size: 1.29 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

suba-sri-72/alu_4bit

4-bit ALU designed in Verilog HDL and verified using QuestaSim.

Language: Verilog - Size: 2.93 KB - Last synced at: 1 day ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

miguelmagv/verilog-flm

⚙️ Simplify Verilog design and simulation with verilog-flm, a lightweight framework that enhances your workflow and boosts productivity.

Size: 1.29 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

Sindhugd6472/apb-uvm-ral

AMBA APB3 slave RTL + verification: wait-state insertion (PREADY), error response (PSLVERR), and self-checking SV tests running on Verilator.

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 1 day ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

enxsni/jquery-tree

🌳 Transform 'ul' and 'li' elements into a collapsible tree view for intuitive file system navigation with this lightweight jQuery library.

Language: CSS - Size: 1.49 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

eunjoon-sung/project

Eunjoon's verilog HDL / C Project 💻

Language: Verilog - Size: 25.3 MB - Last synced at: 5 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0

sukesan7/fpga-risc-core

Synthesizable 8-bit ALU & Control Datapath (RTL) designed for Altera Cyclone II FPGA

Language: VHDL - Size: 214 KB - Last synced at: 7 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0

emrebstc/FPGA-based-Sobel-Edge-Detection-Pipeline-with-VHDL-Simulation-Benchmark

A VHDL implementation of the Sobel edge detection algorithm featuring a 3x3 windowing pipeline with line buffers written for xc7a100tcsg324-1 in Vivado 2025. Also includes a simulation benchmark.

Language: VHDL - Size: 11.7 MB - Last synced at: 9 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0

kirthana1181/Traffic-Signal-Controller

A simple RTL design and logic Synthesis project where I have designed and simulated a traffic signal controller, which regulates traffic signals along NS and EW directions. The top module, the related modules and the testbench, with output waveform simulations are attached in the repo.

Language: Verilog - Size: 162 KB - Last synced at: 9 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

xaashay/hwmodelingusingverilog

Select HDL examples from NPTEL's Hardware Modeling using Verilog

Size: 2.93 KB - Last synced at: 10 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0

VaradaGovind/rtl-spi-controller

Synthesizable Verilog RTL implementation of a full-duplex SPI (Serial Peripheral Interface) Master and Slave. Features configurable clock dividers, Mode 0 (CPOL=0, CPHA=0) timing.

Language: Verilog - Size: 90.8 KB - Last synced at: 12 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0

amirhirx/ecommerce-website

Still under Develepment - Simple e-commerce website with NextJS, TypeScript, TailwindCSS

Language: TypeScript - Size: 13.6 MB - Last synced at: 16 days ago - Pushed at: 19 days ago - Stars: 0 - Forks: 0

Subharthi06/HDL-Bits-Solutions

Collection of the solutions to HDL Bits Problem Sets

Language: Verilog - Size: 136 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

dianluniuniu/async-fifo

Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog

Language: SystemVerilog - Size: 25.4 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

nhoangkiet35/vivado_project

Vivado — Embedded & Digital Design Projects

Language: Verilog - Size: 66.2 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

max-nigri/jpeg_project_2006

Hardware implementation of a JPEG encoder for FPGA/ASIC, developed as an academic project in the Advanced Logic Design course (Hebrew University, 2006–2017). Project by Max Nigri

Language: HTML - Size: 3.93 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

dianluniuniu/clock-management-unit

A comprehensive clock management IP core with multiple divider types and glitch-free switching

Language: Verilog - Size: 25.4 KB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

AmarGelila/Estate-

Estate web app using react and tailwind css, that supports both english and arabic languages

Language: JavaScript - Size: 6.54 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Hithaishisr/Router-1x3

A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.

Language: JavaScript - Size: 15.5 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

PranavR03/mips-pipelined-cpu

A 5-stage pipelined MIPS processor in Verilog

Language: Verilog - Size: 16.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

tom-zv/FPGA-ESP32-Projects

Projects showcase

Language: VHDL - Size: 261 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

mauroxf/verilog-mini-projects

AI generated verilog problems I solved

Language: Verilog - Size: 267 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Sakshipandey04/4-Bit-ALU

Four(4)- bit Arithmetic Logic Unit (ALU) implemented in Verilog with Vivado simulation

Language: Verilog - Size: 226 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Divyanshu-53/Ultrasonic-Sensor-FPGA

Project to interface HC-SR04 ultrasonic sensor with FPGA for distance measurement.

Language: Verilog - Size: 4.17 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

SKpro-glitch/Multi-Bit-Comparator

Variations of a multi-bit generalized magnitude comparator for different area and timing.

Language: D - Size: 275 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

KrishanuDevSarma/Approximate-Comparator-Designs-for-Area-Efficient-Digital-Systems

Area-efficient approximate comparators (4–32 bit) with Verilog RTL, testbenches, and analysis.

Language: Verilog - Size: 248 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

Tamoziit/Computer-Architecture-Organisation-Lab

Vivado VHDL

Language: VHDL - Size: 64.5 KB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

mrxeg1995/yanbu

نقل عفش بينبع

Language: HTML - Size: 8.92 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Subbu-kata/KATA_SUBRAMANYAM_G3_INTEGRATED_VLSI

This project is a fully functional Vending Machine Controller designed using Verilog HDL, featuring modular design, multi-clock domain handling, and APB-based configuration. The system supports both configuration and operation modes, allowing real-time selection, purchase, and dispensing of items based on valid currency input.

Size: 1.95 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

HarmandeepArneja/ReflexRush

Reaction Time Testing Game

Language: Verilog - Size: 0 Bytes - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

VarshithGovi/Logic_gates

Simulate and analyze fundamental logic gates using Icarus Verilog and GTKWave. This project provides a modular Verilog implementation and a comprehensive testbench for precise validation, offering valuable insights into digital design workflows for VLSI professionals.

Language: Verilog - Size: 33.2 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

ViniMF13/Laboratorio_Sistemas_Digitais

Implementação do Projeto Final da Disciplina de Sistemas Digitais, oferecia pelo Departamento de Engenharia Elétrica da UFMG. O Projeto elabora um sistema de cofre digital, seguindo a metodologia de Resgister Transfer Level.

Language: VHDL - Size: 13.6 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

ahmd-kamel/ATM-Bank-Finite-State-Machine

Digital Design & Verification by implementing the core of the bank ATM design as well as verification environment.

Language: C++ - Size: 386 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Haaris-RTL/8-bit-CPU

RTL code of an 8-bit CPU designed in Verilog.

Language: Verilog - Size: 97.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1

Khosravi19/SPA-CodeTime

Single-page application of programming courses using React with a panel and login page

Language: JavaScript - Size: 5.07 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

shahed22/Dadda-8-bit

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

Language: Verilog - Size: 11.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/RV32I_5-Stage_Pipelined_CPU

Processor Design of RV32I 5-Stage Pipelined CPU

Language: SystemVerilog - Size: 170 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/RV32I_Single_Cycle_CPU

Processor Design of RV32I Single Cycle CPU

Language: SystemVerilog - Size: 590 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/AXI4

RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle

Language: Verilog - Size: 19.5 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

cp024s/100-days-of-RTL

probable journey of RTL coding ft. Chandra Prakash

Language: Verilog - Size: 292 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Abdelrahman1810/SPI-Slave-with-Single-Port-RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

Language: Verilog - Size: 600 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/ARTY_A7_I2C_MPU-6050

Integration of Arty A7-100T with MPU-6050 Gyroscope Sensor for Motion Sensing and FPGA Testing

Language: Verilog - Size: 218 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/ARTY_A7_I2C_BME280

Integration of Arty A7-100T with BME280 Pressure Sensor for Pressure Sensing and FPGA Testing

Language: Verilog - Size: 772 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

ZAIN-ALI-02/UART

An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.

Language: Verilog - Size: 4.88 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/SPI

RTL Design of Serial Peripheral Interface

Language: Verilog - Size: 451 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/UART

RTL Design of Universal Asynchronous Receiver-Transmitter

Language: Verilog - Size: 990 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

farukyld/sort-circuit

an RTL circuit that sorts the integer values in a momory unit connected with AXI-Lite

Language: Verilog - Size: 2.5 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

diluo1999/tic_tac_toe

Final project: Tic-tac-toe on VGA monitor. ENGS31/CS56 Digital Electronics @ Dartmouth.

Language: VHDL - Size: 38.9 MB - Last synced at: 6 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

wolfdroid/Integer_Calculator

Simple RTL model for Interger Numbers Calculation using RAM and 7 Segment Display.

Language: VHDL - Size: 1.79 MB - Last synced at: almost 3 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0