Topic: "fpga-programming"
JulianKemmerer/PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Language: VHDL - Size: 76.6 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 668 - Forks: 53
Xilinx/Vitis_Accel_Examples
Vitis_Accel_Examples
Language: Makefile - Size: 107 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 547 - Forks: 217
calyxir/calyx
Intermediate Language (IL) for Hardware Accelerator Generators
Language: Rust - Size: 511 MB - Last synced at: 3 days ago - Pushed at: 5 days ago - Stars: 544 - Forks: 60
cornell-zhang/heterocl
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
Language: Python - Size: 38.7 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 320 - Forks: 93
cornell-zhang/allo
Allo: A Programming Model for Composable Accelerator Design
Language: Python - Size: 4.47 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 255 - Forks: 51
cucapra/dahlia
Time-sensitive affine types for predictable hardware generation
Language: Scala - Size: 5.54 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 145 - Forks: 8
TinyRetroWarehouse/Awesome-Retro-Docs
A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.
Size: 13.8 GB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 142 - Forks: 18
pc2/sus-compiler
A new Hardware Design Language that keeps you in the driver's seat
Language: Rust - Size: 18.7 MB - Last synced at: 4 days ago - Pushed at: 14 days ago - Stars: 114 - Forks: 5
cornell-zhang/HiSparse
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
Language: C++ - Size: 109 MB - Last synced at: 4 months ago - Pushed at: 11 months ago - Stars: 90 - Forks: 10
amaranth-farm/amlib
assorted library of utility cores for amaranth HDL
Language: Python - Size: 251 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 77 - Forks: 13
psychogenic/riffpga
riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way
Language: C - Size: 2.42 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 50 - Forks: 3
cornell-zhang/GraphLily
A graph linear algebra overlay
Language: C++ - Size: 117 MB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 47 - Forks: 2
cornell-zhang/hcl-dialect
HeteroCL-MLIR dialect for accelerator design
Language: C++ - Size: 3.67 MB - Last synced at: 4 months ago - Pushed at: 11 months ago - Stars: 40 - Forks: 15
raetro/sdk-docker-fpga
Intel Quartus Prime Synthesis Engine for Docker
Language: Dockerfile - Size: 847 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 31 - Forks: 7
geraked/verilog-rle
Verilog Implementation of Run Length Encoding for RGB Image Compression
Language: Verilog - Size: 11.6 MB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 25 - Forks: 4
DidierMalenfant/openFPGA-tutorials
A collection of tutorials and resources for the openFPGA platform.
Size: 2.68 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 24 - Forks: 0
ClarkFieseln/FPGA_HW_SIM_FWK_2
FPGA Hardware Simulation Framework
Language: Python - Size: 820 KB - Last synced at: 4 months ago - Pushed at: over 2 years ago - Stars: 22 - Forks: 1
akangakang/OS-ChCore-Lab
上海交通大学软件学院🍭操作系统课程🍦实验
Language: C - Size: 38.5 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 20 - Forks: 12
OpenEDF/verilog-basic
learn the combinational and sequential logic circuit.
Language: SystemVerilog - Size: 24.3 MB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 17 - Forks: 1
jjfumero/tornadovm-examples
Set of examples written for hardware acceleration via TornadoVM
Language: Java - Size: 20.1 MB - Last synced at: 3 months ago - Pushed at: 6 months ago - Stars: 16 - Forks: 4
datacipy/VHDL
Příklady ke knize Data, čipy, procesory
Language: VHDL - Size: 29 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 16 - Forks: 3
ClarkFieseln/FPGA_HW_SIM_FWK
FPGA Hardware Simulation Framework
Language: Python - Size: 2.18 MB - Last synced at: 4 months ago - Pushed at: over 2 years ago - Stars: 15 - Forks: 2
amaranth-farm/amgen
command line tool for frequent amaranth HDL tasks (generate sources, show design)
Language: Python - Size: 251 KB - Last synced at: 22 days ago - Pushed at: over 3 years ago - Stars: 15 - Forks: 2
arasgungore/256-colors-with-VGA
A VHDL-based VGA driver to display 256 different colors on a monitor.
Language: VHDL - Size: 492 KB - Last synced at: 5 months ago - Pushed at: about 3 years ago - Stars: 14 - Forks: 0
fm4dd/gatemate-riscv
RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga
Language: Verilog - Size: 6.18 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 12 - Forks: 2
arasgungore/VGA-based-screensaver Fork of aybaras/VGA-based-screensaver
A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.
Language: VHDL - Size: 494 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 12 - Forks: 0
anupam-io/ES203-COA-CNN
ES-203 Computer Organization & Architecture CNN on FPGA board
Language: Verilog - Size: 16.1 MB - Last synced at: 4 months ago - Pushed at: over 3 years ago - Stars: 12 - Forks: 8
mikeroyal/FPGA-Guide
FPGA Guide
Language: Verilog - Size: 25.4 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 12 - Forks: 2
fpgs/machXOprog
Program Lattice MachXO2/3 with CircuitPython
Language: Python - Size: 46.9 KB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 12 - Forks: 2
Choaib-ELMADI/fpga-programming-for-beginners
A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.
Language: Tcl - Size: 30.4 MB - Last synced at: 5 months ago - Pushed at: 12 months ago - Stars: 11 - Forks: 1
jmduarte/HLS_hls4ml_Tutorial
HLS & hls4ml Tutorial
Language: Jupyter Notebook - Size: 16.9 MB - Last synced at: 4 months ago - Pushed at: about 5 years ago - Stars: 10 - Forks: 6
Kampi/ZYBO
Miscellaneous things and projects for my ZYBO and ZYNQ devices.
Language: VHDL - Size: 545 MB - Last synced at: 4 days ago - Pushed at: almost 2 years ago - Stars: 9 - Forks: 4
jawline/c8hardcaml
An implementation of a CHIP-8 machine for FPGAs in Hardcaml with a custom assembler for writing test programs
Language: OCaml - Size: 646 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 0
santifs/ultrasonic-sensor
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
Language: VHDL - Size: 6.83 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 2
Choaib-ELMADI/getting-started-with-vhdl
Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.
Language: VHDL - Size: 38.5 MB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 7 - Forks: 0
hajin-kim/FPGA_Tutorial_with_HLS
FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS
Language: Tcl - Size: 4.41 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 0
bilalkabas/Basys3-VHDL-Basics
This repository has basic examples in VHDL using Basys3 board.
Language: VHDL - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 5
2268977258/binocular-stitching
基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后通过匹配结果计算拼接参数，完成图像的拼接。
Language: Verilog - Size: 65.5 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 6 - Forks: 0
EngineerMichael/-Robotic-Arm---Haddington-Dynamics-Robotics-Engineering-
⎔ Automation in 3D-Printed Robotics in C & JS (Revising Custom JavaScript Source Code Files)
Language: JavaScript - Size: 4 MB - Last synced at: 4 months ago - Pushed at: 6 months ago - Stars: 6 - Forks: 0
aybaras/VGA-based-screensaver
A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.
Language: VHDL - Size: 494 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 6 - Forks: 2
jamarma/Mecatronica-proyecto
Robot educativo con forma de araña impreso en 3D y controlado a través de una FPGA
Size: 311 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 6 - Forks: 1
cucapra/polyphemus
A Cyclops managing FPGA execution in the clouds
Language: Python - Size: 295 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2
7enTropy7/Artix_7
My experiments with Nexys4 DDR Artix-7 FPGA Board
Language: Verilog - Size: 31.3 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 6 - Forks: 3
styczynski/fpga-verilog
Collection of my projects that was made as a part of Warsaw University FPGA course
Language: Verilog - Size: 441 KB - Last synced at: 2 months ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 0
Choaib-ELMADI/riscv-on-de2-soc-fpga
A simplified RISC-V processor implemented in Verilog and deployed on the DE-2 SoC FPGA board.
Language: Verilog - Size: 24.4 MB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 5 - Forks: 2
Choaib-ELMADI/working-with-fpga-and-mips
A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.
Language: Verilog - Size: 11.2 MB - Last synced at: 2 months ago - Pushed at: 4 months ago - Stars: 5 - Forks: 0
amaranth-farm/amaranth-boards Fork of amaranth-lang/amaranth-boards
Up-to-date board and connector definition files for amaranth HDL
Language: Python - Size: 298 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 1
robseb/rstoolsA10
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA
Language: C++ - Size: 1.27 MB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 2
ziyue-pan/FPGA--JOJO
Final project of Digital Logic Design course, a video game.
Language: VHDL - Size: 62.4 MB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 0
gsteiert-lscc/MachXO_Library
Arduino Library for programming MachXO2/XO3 devices
Language: C++ - Size: 41 KB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 5 - Forks: 4
KietLe11/KLP32-RISCV
This project implements a simple RISC-V processor for FPGAs. It supports the RV32I base instruction set and is designed for educational and experimental purposes.
Language: Verilog - Size: 407 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 4 - Forks: 0
Choaib-ELMADI/working-with-fpga-and-vhdl
A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.
Language: VHDL - Size: 12.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 4 - Forks: 0
robseb/rstoolsCY5
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA
Language: C - Size: 1.74 MB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 5
asankaSovis/Bidirectional_Transmitter
📡 This project was intended to develop a bidirectional transmitter and reciever device that uses Visible Light Communication (VLC) technology to transmit and recieve data from one device to another. In its basic form, data is transmitted as pulses of light where on means bit 1 and off means bit 0.
Language: HTML - Size: 30.1 MB - Last synced at: 5 months ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 0
MichaelBenvenuto/PLDude
A command line utility to generate bitstreams and various programming files easily for PLDs
Language: Python - Size: 108 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0
dineshpinto/timetagger
FPGA programming for nanosecond photon counting
Language: C - Size: 105 MB - Last synced at: 4 months ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 1
micro-FPGA/litex-boards Fork of litex-hub/litex-boards
LiteX boards files
Language: Python - Size: 9.75 MB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 2
benitoss/ZXDOS
Spartan 6 Lx16 Xilinx FPGA board implementing retro 80's 90's machines
Language: VHDL - Size: 55.2 MB - Last synced at: 4 months ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 0
M0JPI/red-pitaya-projects
My Red Pitaya Projects
Language: Jupyter Notebook - Size: 11.1 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 3 - Forks: 1
AkhilRai28/Single-Port-RAM
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
Language: Verilog - Size: 68.4 KB - Last synced at: about 1 month ago - Pushed at: 12 months ago - Stars: 3 - Forks: 0
Hello-FPGA/BISS-C
This is BISS-C FPGA IP and It's Driver Repo
Language: Tcl - Size: 4.85 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0
asankaSovis/eight_bit_computer
🎛️ FPGAs are an interesting invention that is expected to revolutionize the digital industry. This series will focus on building the 8-bit computer that Ben Eater built on his youtube channel. However, it will be done not with actual chips and hardware, but with Verilog code and FPGA simulations.
Language: Verilog - Size: 21.5 KB - Last synced at: 5 months ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1
Divyathali/FPGA-Routing-placement---Best-way
The published IEEE paper tells about the basic details of this project
Language: C - Size: 102 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
rv2442/16BitScientificCalculator
16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board
Language: C - Size: 961 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 2
1c3t3a/canny-zybo-z7
Implementation of a Canny-Edge Detector on a Zybo-Z7 FPGA.
Language: VHDL - Size: 115 MB - Last synced at: 4 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0
talhasevinc/FPGA
FPGA Digital Hardware Design
Language: VHDL - Size: 74.5 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0
AndreasKaratzas/graphics-driver
Custom graphics driver using Verilog on Xilinx FPGA platform.
Language: Verilog - Size: 156 KB - Last synced at: 2 months ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 0
ibrahimalimetin/Robotic-Controller-with-FPGA
Robotic Controller with FPGA
Language: VHDL - Size: 563 KB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 0
ThibaultTricard/Silice-float
32 bits float implementation the FPGA Silice Language
Language: Slice - Size: 55.7 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 0
jgelfman/Dataflow-Based-FPGA-Program-Synthesis-Capstone
An FPGA Program Generator written in Python that takes dsp-sig XML Dataflow Graphs created using FAUST to produce FPGA programs in VHDL.
Language: VHDL - Size: 3.46 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
santifs/simon-game-vhdl
VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.
Language: VHDL - Size: 7.94 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1
AlicePagano/MAPD-A-Project-IPBUS-Filter
FIR filter co-processor implementation in FPGA
Language: VHDL - Size: 40.1 MB - Last synced at: 5 months ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
Vedant2311/Complete-ARM-CPU
Single and Multi-cycle ARM processors implemented using VHDL
Language: VHDL - Size: 354 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
mnb27/Car-Parking-System
Simple car parking system in Verilog
Language: Verilog - Size: 122 KB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 2
FranciscoMotta/VHDL-ADDER
Sumador implementado en VHDL.
Language: VHDL - Size: 1.95 KB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0
ariannagavioli/PNG
A Pseudo-Random Noise Sequence Generator VHDL implementation to synthesize on a Zync FPGA for the Digital Systems Design course of University of Pisa, 2019.
Language: VHDL - Size: 661 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 3 - Forks: 0
sergz72/FPGA
FPGA related stuff
Language: F# - Size: 6.3 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 2 - Forks: 0
lebrancconvas/TypeScript-for-Concept
Clarify anything I'm interested in TypeScript until It can't. (Because TypeScript is good and fit to me for mapping out the domain).
Language: TypeScript - Size: 221 KB - Last synced at: 17 days ago - Pushed at: 19 days ago - Stars: 2 - Forks: 1
Marisa-Mathew/-Image-Edge-Detection-on-FPGA-Sobel-Filter--Verilog
This project implements real-time edge detection on grayscale images using the Sobel filter algorithm, designed in Verilog and simulated in Xilinx Vivado. A sliding 3×3 window is applied to each pixel to compute gradient magnitudes, highlighting object boundaries.
Language: Verilog - Size: 779 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 2 - Forks: 0
Skandakm29/uart_loopback
Universal Asynchronous Receiver-Transmitter (UART) loopback on the VSD Squadcom Mini FPGA board
Language: Verilog - Size: 5.45 MB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 2 - Forks: 0
SKpro-glitch/Parallel_Multiplier
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
Language: SystemVerilog - Size: 17.6 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 2 - Forks: 0
Wissance/QuickRS232
A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX
Language: Verilog - Size: 739 KB - Last synced at: 4 months ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0
Slatyo/SonarTracking
Small project to track things with a waterproof sonar sensor
Language: C++ - Size: 2.22 MB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
rejunity/fpga-icebreaker-racing-the-beam
Playground for graphics experiments running on iCE40 Lattice FPGA with iceBreaker board
Language: Verilog - Size: 40 KB - Last synced at: 8 days ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1
n-roussos/A-framework-for-developing-Neural-Networks-in-hardware-accelerators Fork of georgevangelou/A-framework-for-developing-Neural-Networks-in-hardware-accelerators
This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.
Language: C - Size: 25 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
Tauheed-Elahee/FPGA-Stopwatch
Impement a simple stopwatch on an FPGA. There is an added goal of making as many modules paramterized as possible and sticking to structural code as much as possible.
Language: Verilog - Size: 255 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
abdalla1912mohamed/-AES-encryption-and-decryption-platform-in-FPGA-communication
implementing a protected communication platform between 2 FPGA's. Data is entered through a keyboard-FPGA interface then the data is encrypted using AES encryption and sent to the second FPGA where the decryption occurs if the decryption key is given and the data is displayed using an FPGA-LCD interface using VHDL scripts
Language: C - Size: 1.14 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0
AhmadrezaHadi/MIPS-Architecture-Using-Verilog
FPGA Final Project
Language: C - Size: 1020 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0
Mohamed-Adil-Cyber/FPGA_CycloneIV_ep4ce6e22c8n_Electrical_Pulse
Simple electrical pulse preferably for LEDs made for cyclone IV with image examples
Language: VHDL - Size: 262 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0
mukullokhande99/fifo_hardware_fpga
FIFO implemented on FPGA Spartan 6
Language: Rich Text Format - Size: 21.4 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 1
DuinOS/AprendaFPGA
Algumas anotações de quem está aprendendo a sintetizar seu próprio microcontrolador em FPGA.
Size: 23.4 KB - Last synced at: 2 days ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0
Harshp1802/Fake-Currency-Detector
Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB
Language: VHDL - Size: 27.4 MB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 2
einstein07/Yoda
(Your Own Digital Accelerator) A Smoothing filter by using a Finite Impulse Response (FIR) and a Low Pass Filter (LPF) algorithm. The hardware used is a NEXYS A7 Field Programmable Gate Array (FPGA) programmedin Verilog.
Language: VHDL - Size: 13.8 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 3
topologicalhurt/Thesis
Fpga thesis project. An intelligent hardware scheduling algorithm focused on common signal chains.
Language: SystemVerilog - Size: 130 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1 - Forks: 0
Unicamp-Odhin/FPGA_101
Starting in the world of FPGAs!!!!!
Language: Tcl - Size: 18.6 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1 - Forks: 0
Zachary-Pearce/Pomegranate
An open source portable and scalable soft-core processor written in VHDL.
Language: VHDL - Size: 2.34 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0
jorgeloopzz/Practicas-HP
Prácticas de laboratorio de la asignatura Hardware Programable
Language: Tcl - Size: 1.66 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
enriiexposed/das-fdi
Asignatura optativa de la FDI - UCM sobre el diseño de circuitos de tamaño medio usando herramientas de descripcion de hardware automáticas (VHDL, Verilog sobre Vivado)
Language: VHDL - Size: 165 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
pboechat/ice40up5k_riscv Fork of emeb/up5k_riscv
RISC-V SoC on the iCE40UP5K.
Language: C - Size: 540 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
aidinattar/PMOD-FIR-filter-VHDL
Implementation of a FIR-filter on a FPGA and its employment in an audio system obtained using a PMOD I2S2.
Language: SystemVerilog - Size: 91.9 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 1
