Topic: "vhdl-code"
alialaei1/HDLab-FPGA-Development-Board
Open source FPGA development platform
Language: VHDL - Size: 21.6 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 46 - Forks: 22
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
Language: VHDL - Size: 2.52 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 27 - Forks: 5
ClarkFieseln/FPGA_HW_SIM_FWK_2
FPGA Hardware Simulation Framework
Language: Python - Size: 820 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 22 - Forks: 1
sarthak268/Embedded_Logic_and_Design
This repository contains all labs done as a part of the Embedded Logic and Design course.
Size: 14.7 MB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 21 - Forks: 2
datacipy/VHDL
Příklady ke knize Data, čipy, procesory
Language: VHDL - Size: 29 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 16 - Forks: 3
ClarkFieseln/FPGA_HW_SIM_FWK
FPGA Hardware Simulation Framework
Language: Python - Size: 2.18 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 15 - Forks: 2
arasgungore/256-colors-with-VGA
A VHDL-based VGA driver to display 256 different colors on a monitor.
Language: VHDL - Size: 492 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 14 - Forks: 0
mcagriaksoy/VHDL-FPGA-LAB_PROJECTS
My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)
Language: VHDL - Size: 575 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 14 - Forks: 2
arasgungore/VGA-based-screensaver Fork of aybaras/VGA-based-screensaver
A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.
Language: VHDL - Size: 494 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 12 - Forks: 0
akaeba/tinyUART
Lightweight UART core in VHDL
Language: VHDL - Size: 444 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 11 - Forks: 2
Charlie5DH/RISC-V-Single-Cycle-uP
Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture
Language: VHDL - Size: 82.2 MB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 11 - Forks: 1
akaeba/generic_spi_master
Customizable multi chip select supporting Serial Peripheral Interface master.
Language: VHDL - Size: 729 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 10 - Forks: 0
JulyWitch/vhdl_ghdl_examples
Simple VHDL examples using ghdl as compiler and wave generating
Language: VHDL - Size: 396 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 9 - Forks: 0
abdelazeem201/Arm-Core
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
Language: C - Size: 6.94 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 8 - Forks: 1
mrtkp9993/VHDLExamples
VHDL examples.
Language: VHDL - Size: 39.1 KB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 0
BertVerrycken/BERT
Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)
Language: VHDL - Size: 52.7 KB - Last synced at: 6 months ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 1
santifs/ultrasonic-sensor
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
Language: VHDL - Size: 6.83 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 2
Kazhuu/audio-synthesizer
Copy of old FPGA audio synthesizer project for DE2 development board
Language: VHDL - Size: 4.76 MB - Last synced at: 21 days ago - Pushed at: over 6 years ago - Stars: 8 - Forks: 0
Choaib-ELMADI/getting-started-with-vhdl
Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.
Language: VHDL - Size: 38.5 MB - Last synced at: 6 days ago - Pushed at: 3 months ago - Stars: 7 - Forks: 0
akaeba/eSpiMasterBfm
Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master
Language: VHDL - Size: 287 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 7 - Forks: 3
tocache/Altera-Cyclone-II-FPGA
Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II
Language: C - Size: 229 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 7 - Forks: 1
s-gbz/VHDL-exercises-examples
Code examples from the Technical Computer Science (Technische Informatik) module.
Language: VHDL - Size: 3.12 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 7 - Forks: 1
nazaninsbr/Neural-Network
Neural Network with VHDL and matlab
Language: C - Size: 18.9 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 7 - Forks: 3
elbekka/Programacion-De-Hardware-VHDL
4 bits ALU with 2 entries of selection using structural vhdl
Language: VHDL - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 7 - Forks: 1
aybaras/VGA-based-screensaver
A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.
Language: VHDL - Size: 494 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 2
romybompart/Basys3-clock-alarm-with-buzzer
Digital clock implemented in vhdl for the Basys 3 Board from Digilent.
Language: VHDL - Size: 177 KB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 0
arxiver/Pipelined-MIPS
MIPS Pipelined CPU simulation using VHDL language
Language: VHDL - Size: 1.53 MB - Last synced at: 4 days ago - Pushed at: about 5 years ago - Stars: 6 - Forks: 0
AliceO2Group/alice-fit-fpga
ALICE Fast Interaction Trigger (FIT) FPGA code
Language: VHDL - Size: 32.2 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 4
mongrelgem/cMIPS
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
Language: Verilog - Size: 4.09 MB - Last synced at: 4 months ago - Pushed at: over 5 years ago - Stars: 5 - Forks: 0
akgokce/dungeon-escape-vhdl-game
Dungeon Escape VHDL Game
Language: VHDL - Size: 91.8 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 5 - Forks: 0
Choaib-ELMADI/working-with-fpga-and-vhdl
A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.
Language: VHDL - Size: 12.4 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 4 - Forks: 0
manish-9245/VHDL-Programs
This repository contains VHDL files of different Digital Designs.
Language: VHDL - Size: 4.49 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 0
Alexdruso/Progetto-di-reti-logiche-2019
A VHDL project for the "Digital logic design" course 2020
Language: VHDL - Size: 9.28 MB - Last synced at: 2 months ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 0
parsa-k/ALU-32bit
32-bit line ALU that can operate 24 functions, implemented in VHDL.
Language: VHDL - Size: 7.81 KB - Last synced at: 11 months ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 0
Steve-Teal/pumpkin-cpu
A small general purpose, scalable, 16-bit, 16 instruction CPU core written in VHDL
Language: C - Size: 83 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0
tirtharajsinha/vhdl_codes
vhdl
Language: VHDL - Size: 9.77 KB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 4 - Forks: 0
benitoss/ZXDOS
Spartan 6 Lx16 Xilinx FPGA board implementing retro 80's 90's machines
Language: VHDL - Size: 55.2 MB - Last synced at: about 2 months ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 0
soumyadip007/VHDL-Modelsim-Altera-Simulator-COA
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
Size: 78.1 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 1
micro-FPGA/meM
micro embedded Matrix
Language: VHDL - Size: 51.8 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 2
BDSM-hardware/lock_handler
Manages multi points bondage locks, for self or collective bondage.
Language: PostScript - Size: 2.85 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 0
Var7600/VHDL-GENERATOR
App that Generate VHDL Code and Testbench template file
Language: HTML - Size: 7.15 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 0
EngineerMichael/ModelSim-Altera-Project-Electronics-
⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.
Size: 25.4 KB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 0
bryan-hoang/elec-271-digital-systems-labs 📦
VHDL Code for Labs done in a 2nd year engineering Digital Systems course (ELEC 271) at Queen's University.
Language: VHDL - Size: 10.7 KB - Last synced at: 10 days ago - Pushed at: 6 months ago - Stars: 3 - Forks: 1
LeHack/SPSP
Particulate matter pollution monitoring system (:poland: System Pomiaru Stężenia Pyłu w powietrzu)
Language: VHDL - Size: 5.52 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1
jagumiel/irReceiver
Remote control infrared signal receiver programmed in VHDL for a Terasic DE1-SoC board.
Language: VHDL - Size: 7.55 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 3
talhasevinc/FPGA
FPGA Digital Hardware Design
Language: VHDL - Size: 74.5 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0
idataaki/vhdl-projects
all projects of vhdl course of university
Language: VHDL - Size: 883 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0
obih9/Progetto-Reti-Logiche-2021
Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - a.a. 2020-2021
Language: VHDL - Size: 1.63 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0
santifs/simon-game-vhdl
VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.
Language: VHDL - Size: 7.94 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1
AlicePagano/MAPD-A-Project-IPBUS-Filter
FIR filter co-processor implementation in FPGA
Language: VHDL - Size: 40.1 MB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
lucaleoni7/project-retilogiche
Final Project - Reti Logiche. Politecnico di Milano, A.A. 2019-2020
Language: VHDL - Size: 782 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1
FranciscoMotta/VHDL-ADDER
Sumador implementado en VHDL.
Language: VHDL - Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 0
HembramBeta777/Digital-Logic-assignment-
VHDL___programming
Size: 38.1 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0
Megapiro/Progetto-RETI-2019
Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - a.a. 2018-2019
Language: VHDL - Size: 323 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 3
Stavros/Multiplier4bit
A 4bit Multiplier in VHDL
Language: VHDL - Size: 2.94 MB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 1
ariannagavioli/PNG
A Pseudo-Random Noise Sequence Generator VHDL implementation to synthesize on a Zync FPGA for the Digital Systems Design course of University of Pisa, 2019.
Language: VHDL - Size: 661 KB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 3 - Forks: 0
tertiarycourses/FPGATraining
Exercise files for VHDL Programming Training for FPGA
Language: VHDL - Size: 6.84 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 3 - Forks: 0
berkaybarlas/VHDL-Clock-Project
⏰ A Fully Functional Clock with alarm and snooze .
Language: VHDL - Size: 7.81 KB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 2
Daymorelah/vendingMachine
A simple VHDL code that describes the hardware needed to implement a vending machine
Language: VHDL - Size: 485 KB - Last synced at: 6 months ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 1
Saradwata-Bandyopadhyay/VHDL_Codes_Forum
VHDL (VHSIC-HDL, Very High Speed Integrated Circuit Hardware Description Language) is a hardware description language. This is a dummy website built using Bootstrap, PHP and MySQL.
Language: PHP - Size: 1.19 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0
Saeed-dev2/Saeed-dev2
Config files for my GitHub profile.
Size: 22.5 KB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0
kamplianitis/SingleCycleProcessor
Single cycle processor Design for the purposes of the course Computer Organisation at Technical University of Crete (TUC)
Language: VHDL - Size: 261 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 2
jagumiel/Data-Acquisition
This repository contains some examples of data acquisition over MATLAB, LabVIEW and VHDL.
Language: C - Size: 399 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0
onegentig/VUT-FIT-INC2022-projekt 📦
Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022
Language: VHDL - Size: 255 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
abdalla1912mohamed/-AES-encryption-and-decryption-platform-in-FPGA-communication
implementing a protected communication platform between 2 FPGA's. Data is entered through a keyboard-FPGA interface then the data is encrypted using AES encryption and sent to the second FPGA where the decryption occurs if the decryption key is given and the data is displayed using an FPGA-LCD interface using VHDL scripts
Language: C - Size: 1.14 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
Suvraneel/VHDL-Xilinx
Projects were generated in Xilinx v14.7 If you're using Xilinx you may simply import the projects. Otherwise just read the codes in .vhd extensioned files. ☮️
Language: C - Size: 9.47 MB - Last synced at: 2 days ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
touunix/RS-232-standard-handling-VHDL
RS-232 standard handling VHDL | Obsługa portu RS-232
Language: VHDL - Size: 9.77 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
touunix/Johnson-code-counter-VHDL
Johnson code counter VHDL | Licznik w kodzie Johnsona VHDL
Language: VHDL - Size: 496 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
ZahraAbtahi/8_Bit_VHDL_Project
Language: VHDL - Size: 386 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
VXAPPS/cmake-ghdl-compiler
GHDL Compiler Definition for CMake
Language: CMake - Size: 32.2 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0
BojanFaletic/fpga_ip
Collection of IP used in projects
Language: VHDL - Size: 9.68 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0
pat0s/vut-inc-project
Príjem a zasielanie dát na asynchrónnej sériovej linke
Language: VHDL - Size: 277 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0
Azzedine-prog/STOP-WATCH-AND-RTC-FPGA-FULL-PROJECT
STOP WATCH AND RTC FPGA FULL PROJECT
Language: VHDL - Size: 17.6 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1
haideraheem/Programming-FPGA-Basys3-with-VHDL
This repository contains beginner to intermediate level of codes for VHDL and Basys 3.
Size: 6.53 MB - Last synced at: 5 months ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 1
zrajani/Fundamentals-of-Digital-Design-Using-VHDL
VHDL Codes to Implement Concepts of Digital Electronics
Language: VHDL - Size: 316 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 0
Stavros/FSM_CarAlarm
Finite-State Machine Design of a Simple Car Security Alarm on FPGA
Language: VHDL - Size: 39.1 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0
Tanmaymundra/vhdl
This repository contains example of logic such as comparator, encoder, etc in vhdl. Feel Free to add other examples in this repository
Language: VHDL - Size: 76.2 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0
shahjui2000/Push-Button-Door-VHDL-
Simulation of a push button door lock with a variable password
Size: 160 KB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1
DantasB/hangman-game-vhdl
A simple Hangman game made using VHDL
Language: VHDL - Size: 611 KB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 0
DantasB/ula-vhdl
A simple ULA made using VHDL
Language: VHDL - Size: 1.92 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 1
pronoym99/PN-Sequence-Generator
This is a simulation based VHDL code developed in Xilinx to demonstrate a 4-bit PN sequence generator.
Language: C++ - Size: 2.38 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0
swapnilbembde/aes_128
VHDL Implementation of AES-128
Language: VHDL - Size: 43 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 5
Sanchit-20/Ten_Bit_Multiplier
Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.
Language: VHDL - Size: 777 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0
aidinattar/PMOD-FIR-filter-VHDL
Implementation of a FIR-filter on a FPGA and its employment in an audio system obtained using a PMOD I2S2.
Language: SystemVerilog - Size: 91.9 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 1
Var7600/VHDL93-Docset
The VHDL93 Docset provides offline access to VHDL-93 documentation for users of Zeal and Dash. This docset includes syntax references, examples, and explanations of key VHDL concepts.
Language: HTML - Size: 268 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
ZIKOAR/32-bit-processor-with-vhdl
A 32-bit VHDL processor with 26 instructions, including jumps, branches, and function calls. Implementing an FSM for execution control and testing using Quartus and ModelSim.
Language: VHDL - Size: 6.84 KB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 1
JN513/fpga_basics
Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog
Language: Verilog - Size: 59.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
Husseinabdo2003/Traffic_System
The project was about creating a traffic light system using microcontrollers and sensors using VHDL Programing Language. The FPGA used is basys 3, Ultrasonic sensor, DHT11 sensor, LCD, and a buzzer.
Size: 5.96 MB - Last synced at: 16 days ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0
el3ctrician/lfsr
A vhdl device to generate random numbers LFSR
Language: VHDL - Size: 2.93 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0
HumbertoCG18/PUCRS-FSD-2.3-2023.24
Trabalhos, Projetos, Exercícios e aulas realizados em VHDL e Assembly na cadeira de Fundamentos de sistemas digitais, matéria do segundo semestre.
Language: VHDL - Size: 949 KB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0
Aom92/FPGA-Effects-Pedal
Proyecto de Tesis donde se realiza procesamiento digital de audio para hacer una pedalera de efectos de guitarra con la FPGA DE10-Lite
Language: Jupyter Notebook - Size: 210 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0
mazen-daghari/VHDL-AMS-Sonde
description d'un capteur ECG a base de VHDL-AMS (SIMPLORER V7)
Language: Brightscript - Size: 1.95 MB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
alessda/door_lock
Language: C - Size: 1.56 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
AzazHassankhan/VHDLCodeCraft
Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐
Size: 182 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
onegentig/VUT-FIT-INP2022-projekt1 📦
První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023
Language: VHDL - Size: 2.42 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
seigtm/circuitry-spbpu-homework
This repository is dedicated to storing and managing homework assignments for the course "Digital Circuit Design: Modeling and Description Languages." The assignments primarily involve VHDL source code.
Language: VHDL - Size: 8.79 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
farbodfld/CoDesign-Course
Projects of CoDesign course at SBU
Language: VHDL - Size: 3.86 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
francescospangaro/ProgettoRL
Prova finale di Reti Logiche A.A. 2022/2023
Language: VHDL - Size: 5.33 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 1
IgnacioChirinos/MIPS-VHDL-Vivado
MIPS processor that performs matrix multiplication 3x3 based on VHDL and implemented in XILINX
Language: VHDL - Size: 296 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
hk-117/VHDL
Some example of vhdl code, using ghdl and gtkwave.
Language: VHDL - Size: 30.3 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
