mikeroyal/VHDL-Guide

VHDL Guide

Language: VHDL - Size: 135 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 62 - Forks: 8

alirezakay/RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Language: VHDL - Size: 2.52 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 27 - Forks: 5

santifs/ultrasonic-sensor

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

Language: VHDL - Size: 6.83 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 2

tocache/Altera-Cyclone-II-FPGA

Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II

Language: C - Size: 229 MB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 7 - Forks: 1

vedranMv/axi_spi_master

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

Language: VHDL - Size: 27.3 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 7 - Forks: 0

djcopley/vga_module

VHDL VGA-Display Module

Language: VHDL - Size: 44.9 KB - Last synced at: 8 days ago - Pushed at: 10 months ago - Stars: 5 - Forks: 1

Davide-DD/text-controller

Show phrases on VGA displays fast and easily (using a framebuffer)

Language: VHDL - Size: 19.5 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 0

manish-9245/VHDL-Programs

This repository contains VHDL files of different Digital Designs.

Language: VHDL - Size: 4.49 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 0

Var7600/VHDL-GENERATOR

App that Generate VHDL Code and Testbench template file

Language: HTML - Size: 7.15 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 0

idataaki/vhdl-projects

all projects of vhdl course of university

Language: VHDL - Size: 883 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

santifs/simon-game-vhdl

VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.

Language: VHDL - Size: 7.94 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

HembramBeta777/Digital-Logic-assignment-

VHDL___programming

Size: 38.1 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0

Cat-Gawr/AI-Python

Una piccola AI che il suo picco massimo di risposta è stato di 0.02 secondi di risposta | Konata ~ 2025

Language: Python - Size: 863 KB - Last synced at: 21 days ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

ZahraAbtahi/8_Bit_VHDL_Project

Language: VHDL - Size: 386 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

haideraheem/Programming-FPGA-Basys3-with-VHDL

This repository contains beginner to intermediate level of codes for VHDL and Basys 3.

Size: 6.53 MB - Last synced at: 6 months ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 1

jeandet/VHD_Lib

LPP's VHD_Lib is a kind of addon to gaisler's grlib with most Laboratory of Plasma Physics VHDL IPs.

Language: VHDL - Size: 68.1 MB - Last synced at: 2 months ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

pronoym99/PN-Sequence-Generator

This is a simulation based VHDL code developed in Xilinx to demonstrate a 4-bit PN sequence generator.

Language: C++ - Size: 2.38 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

Sanchit-20/Ten_Bit_Multiplier

Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.

Language: VHDL - Size: 777 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

el3ctrician/lfsr

A vhdl device to generate random numbers LFSR

Language: VHDL - Size: 2.93 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

MatheusAndrade23/E08-L2-Project

Repositório do projeto da matéria de Laboratório de Digital II.

Language: VHDL - Size: 1.24 MB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

farbodfld/CoDesign-Course

Projects of CoDesign course at SBU

Language: VHDL - Size: 3.86 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

hk-117/VHDL

Some example of vhdl code, using ghdl and gtkwave.

Language: VHDL - Size: 30.3 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

DoCodeForever/vhdl

Size: 535 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Deadline-Design/VHDL

VHDL repository that hopefully is of broad use

Language: VHDL - Size: 84 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

ivochan/VHDL-Exercises

digital electronics components implementation in VHDL

Language: VHDL - Size: 41.6 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

martin-garaj/quad_soc

Quadcopter project on Cyclone-V.

Language: C++ - Size: 22 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 1

lucagrammer/Working-Zone

Final Project - Reti Logiche. Politecnico di Milano, A.A. 2019-2020

Language: VHDL - Size: 6.55 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

CodexLink/Time-Based-Clap-Pattern-Lock-VHDL08

A Time-Based Clap Lock Mechanism in Lower-Level Machine Implementation. Created by 4-Member Team VHDL Project in CPE 016 — Introduction to VHDL | Implemented in HDL 2008.

Language: VHDL - Size: 688 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

KishanJ29/FFLDecTasks

VHDL Primer at FLD

Language: VHDL - Size: 438 KB - Last synced at: 11 months ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

ckevar/IIR-Filter

IIR Filter for audio application

Language: VHDL - Size: 10.7 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 4

asl0007/DSD-VHDL-

PROGRAMS OF VHDL

Language: VHDL - Size: 2.26 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

ebangris/First-Processor

ProgramCounter implemented in vhdl

Language: VHDL - Size: 47.9 KB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

MateiB20/Proiect-n-echip-electronic-digital-

Counter– Registru Paralel

Language: Tcl - Size: 796 KB - Last synced at: 22 days ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

MohammedS2lah/Digital_Design_With_VHDL

In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.

Language: VHDL - Size: 36.1 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

mohammadamintahmasbi/AMA-Cach-RAM

Final project of VHDL lession, AMA Cach-RAM

Language: C - Size: 3.92 MB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

rowantwilley16/digital-systems-vhdl

A library of common VHDL components

Language: VHDL - Size: 10.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Davide-Ettori/Memory_Interaction-Hardware-Component-FPGA

Digital Circuits Design Project (PoliMi, year 2022) - Memory Interaction

Language: VHDL - Size: 7.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

lorenzozaccomer/iterative-multiplier

Project for Electronic Calculators course.

Language: VHDL - Size: 4.77 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

EliaFantini/ContrastEQ-VHDL-module-of-a-contrast-equalizer-for-FPGAs

VHDL module of a contrast equalizer to be implemented on FPGAs

Language: VHDL - Size: 638 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

MusicalTester63/digital-electronics-1

VHDL course at Brno University of Technology

Language: VHDL - Size: 25.3 MB - Last synced at: 6 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

chkrr00k/hex-controller

Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board

Language: VHDL - Size: 6.84 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

chkrr00k/sram-controller

A simple sram controller and test for the altera DE1 FPGA board

Language: VHDL - Size: 15.6 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 2

tmessini/vhdl-mobile-ipv6

VHDL Implementation of Mobile IPv6

Size: 1.79 MB - Last synced at: 4 months ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

AmelBENAIDA/Afficheur-7-segments-VHDL

Ce projet est un programme VHDL qui permet d'afficher les chiffres Hexadécimals (0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F)

Language: HTML - Size: 94.7 KB - Last synced at: about 1 year ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0

tdurkut/BIL331

Bilgisayar Organizasyonu Verilog Projeleri

Language: Verilog - Size: 2.08 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0

J-Rios/VHDL_Modules

VHDL modules recopilation. From basic examples to advanced structures and features, through combinational and secuencial systems implementations.

Language: VHDL - Size: 145 KB - Last synced at: about 1 year ago - Pushed at: over 8 years ago - Stars: 0 - Forks: 0