gtkwave | Topic | Ecosyste.ms: Repos

Topic: "gtkwave"

buserror/simavr

simavr is a lean, mean and hackable AVR simulator for linux & OSX

Language: C - Size: 5.65 MB - Last synced at: 7 days ago - Pushed at: 10 days ago - Stars: 1,635 - Forks: 375

yne/vcd

VCD file (Value Change Dump) command line viewer

Language: C - Size: 239 KB - Last synced at: 19 days ago - Pushed at: over 2 years ago - Stars: 116 - Forks: 12

dpretet/svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Language: Python - Size: 755 KB - Last synced at: 7 days ago - Pushed at: 6 months ago - Stars: 77 - Forks: 17

IBM/hdl-tools 📦

Facilitates building open source tools for working with hardware description languages (HDLs)

Language: Perl - Size: 40 KB - Last synced at: 4 months ago - Pushed at: over 5 years ago - Stars: 62 - Forks: 12

ghdl/docker

Scripts to build and use docker images including GHDL

Language: Shell - Size: 250 KB - Last synced at: 18 days ago - Pushed at: 5 months ago - Stars: 42 - Forks: 11

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.7 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 36 - Forks: 11

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Language: SystemVerilog - Size: 432 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 35 - Forks: 2

albertxie/iverilog-tutorial

Quickstart guide on Icarus Verilog.

Language: Verilog - Size: 119 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 32 - Forks: 9

Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

Language: Java - Size: 3.39 MB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 15 - Forks: 1

umarcor/SIEAV

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

Language: VHDL - Size: 9.1 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 13 - Forks: 6

machitgarha/parvaj

Easy and fast VHDL simulation tool, integrating GHDL and GTKWave

Language: PHP - Size: 241 KB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 11 - Forks: 1

TheOneKevin/icarusext

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

Language: TypeScript - Size: 586 KB - Last synced at: 3 days ago - Pushed at: about 2 years ago - Stars: 11 - Forks: 3

cclienti/wavedisp

Python classes to create agnostic wave files for HDL simulator viewer

Language: Python - Size: 126 KB - Last synced at: 1 day ago - Pushed at: about 5 years ago - Stars: 11 - Forks: 1

arhamhashmi01/rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Language: Verilog - Size: 357 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 10 - Forks: 0

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2

bluecmd/fst-example

Example how to use the Fast Signal Trace (FST) format and library

Language: C - Size: 113 KB - Last synced at: 28 minutes ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 1

five-embeddev/riscv-gtkwave

GTKWave Decoders for RISCV

Language: C++ - Size: 463 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 7 - Forks: 0

agoessling/rules_verilog

Utilities for working with Verilog within Bazel.

Language: Python - Size: 6.84 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 1

GLADICOS/UART

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

Language: Verilog - Size: 352 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 1

edaa-org/pyEDAA.ToolSetup

Language: Python - Size: 2.82 MB - Last synced at: 4 days ago - Pushed at: 3 months ago - Stars: 5 - Forks: 0

maazm007/vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Language: C - Size: 5.79 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 5 - Forks: 0

Didula98/Building-a-Simple-Processor

Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL

Language: Verilog - Size: 7.97 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 0

arjunrajasekharan/16-bit-DADDA-Multiplier

16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

Language: Verilog - Size: 27.3 KB - Last synced at: 11 months ago - Pushed at: almost 4 years ago - Stars: 5 - Forks: 0

YoussefRaafatNasry/vhdl-docker-template

Template for creating VHDL project using docker

Language: VHDL - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 5 - Forks: 1

dbhi/containers

Containerized open and free development tools for Dynamic Binary Hardware Injection (DBHI)

Language: Dockerfile - Size: 123 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 1

johannesbonk/vscode-ghdl-interface

A tool to invoke ghdl/gtkwave functions, including error highlighting

Language: JavaScript - Size: 16.1 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 5

arjunrajasekharan/16bit-Sklansky-Adder

16-bit Slansky Adder design using verilog HDL

Language: Verilog - Size: 361 KB - Last synced at: 11 months ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 1

muhammadtalhasami/RV32I_Single_Cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Language: Verilog - Size: 168 KB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0

GLADICOS/SPACEWIRESYSTEMC

This is a test suit spacewire using a model on systemC with a verilog with graphical interface

Language: PHP - Size: 650 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1

shushantkumar/Encryption-Decryption-Model

A completely functional encryption decryption model with specially generated Asymmetric key verification

Language: Verilog - Size: 557 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 3 - Forks: 4

brown9804/VerilogCircuitDesignsHub

Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.

Language: Verilog - Size: 4.76 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

STjurny/SymbolEx

Tool for extracting symbols from Verilog source for displaying in GTKWave.

Language: C++ - Size: 107 KB - Last synced at: 1 day ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

VicoHBB/Verilator-SV-Template

This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.

Language: SystemVerilog - Size: 62.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

kambadur/Projects

Everything related to MCUs, FPGAs, C, Verilog, Matlab/Simullink

Language: C - Size: 72.5 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

Varunkumar0610/RISC-V-32I-5-stage-Pipeline-Core

Implementation of 5 Stage 32I RISC V Pipeline Processor.

Language: Verilog - Size: 1.44 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

Alfredosavi/tangnano-hello

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

Language: Makefile - Size: 8.79 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 1

embed-dsp/ed_gtkwave

Compile and Install of GTKWave Tool (Waveform viewer for LXT, LXT2, VZT, FST, GHW, VCD and EVCD files)

Language: Makefile - Size: 20.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 1

Ammar-Bin-Amir/Verilog_Practice

Practice Codes of Verilog Language

Language: Verilog - Size: 1.4 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

muhammadtalhasami/verilog_practice

Verilog is a hardware description language. This repo is basically a learning journey of verilog

Language: Verilog - Size: 5.86 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

smsraj2001/RING-AND-JOHNSONS-COUNTER

An iverilog program displaying the working of RING and JOHNSONS counter with the Timing diagram in GTK wave.

Language: Verilog - Size: 8.79 KB - Last synced at: 2 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

ramachandra2002/RTL-design-using-Verilog-with-SKY130-Technology

This Repository consists of the report and notes from the workshop RTL design with Verilog with SKY130 Technology conducted by VLSI System Design Pvt. Ltd.

Size: 10.6 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

zhouxs1023/setup_script

setup script for iverilog+gtkwave by inno setup

Language: Inno Setup - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

asl0007/DSD-VHDL-

PROGRAMS OF VHDL

Language: VHDL - Size: 2.26 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

gnalexandridis/FIFO_HUA-MCA-2016-2017

This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University.

Language: Verilog - Size: 577 KB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

mkfahim/Iverilog-GTKWave

Verilog simulations with Icarus Verilog and waveform display via GTKWave

Size: 0 Bytes - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

AbinashDwibedi/learning-verilog

A repository dedicated to learning Verilog, featuring examples, testbenches, simulations, and gate-level designs. Perfect for beginners and enthusiasts exploring hardware description languages.

Language: Verilog - Size: 1.35 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

VarshithGovi/Logic_gates

Simulate and analyze fundamental logic gates using Icarus Verilog and GTKWave. This project provides a modular Verilog implementation and a comprehensive testbench for precise validation, offering valuable insights into digital design workflows for VLSI professionals.

Language: Verilog - Size: 33.2 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

VarshithGovi/Half-Subtractor-Design-Verilog

Gate-level implementation of a half-subtractor using Verilog, featuring a comprehensive testbench, truth table validation, and waveform analysis for beginners in digital design.

Language: Verilog - Size: 20.5 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

VarshithGovi/2bit-Ripple-Carry-Adder-Verilog

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

Language: Verilog - Size: 25.4 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

VarshithGovi/Full-Adder-Design-Verilog

Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

Language: Verilog - Size: 11.7 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

VarshithGovi/Half-Adder-Design-Verilog

A compact Verilog project implementing a half-adder with gate-level modeling, featuring a detailed testbench for functional verification and simulation.

Language: Verilog - Size: 23.4 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

prabalraj18/Adder

This repository contains Verilog implementations and testbenches for various types of adders, ranging from basic to advanced designs. Each adder is verified using testbenches and follows a structured approach to digital circuit design.

Size: 4.88 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

antsiri/Elaborato_di_Architettura_dei_Sistemi_Digitali

Elaborato ADSi - Proff. Nicola Mazzocca - Alessandra De Benedictis

Language: VHDL - Size: 106 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

binzakens/ET1_DT5-EFI-20231

This is an indie Electronic Fuel Injection System project that's been inherited from our sensẽi, Mr NQA. This project is a big bravo to the rest of my teammate, we've all been trying to do our best and we do.

Language: C - Size: 34.7 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

VarshithGovi/2-to-1-Multiplexer-Design-Verilog

Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

Language: Verilog - Size: 17.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Daedalus-op/ALU

An ALU build from scratch. With FPGA and ASIC implementation

Language: Verilog - Size: 1.28 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

arjun-mec/Digital-Combination-Lock

Verilog Implementation of a Digital Combinational Lock which unlocks when a specific 3 bit sequence is entered.

Language: Verilog - Size: 134 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

watbulb/tt-toolchain-build

A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)

Language: Shell - Size: 60.5 KB - Last synced at: 7 days ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

dominiksalvet/super-riscv

Superscalar dual-issue RISC-V processor

Language: SystemVerilog - Size: 1.78 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

tiagosr/wavefront

Waveform plot visualizer in HTML5, using React, Vite and Electron

Language: TypeScript - Size: 61.5 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

sakthispgs/VSDsquadronmini_intern

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Size: 749 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

VijayN53/VSDSquadron_Mini_Internship

This repository contains all the task done during the VSDSquadron Mini internship 2024

Language: C - Size: 8.08 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

BhattSoham/RISCV-HDP

Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)

Language: Verilog - Size: 42.7 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

codingwthisa/Procesador-Monociclo-RISCV

Implementación del procesador monociclo RISC-V en System Verilog.

Language: SystemVerilog - Size: 31.3 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

Pa1mantri/VSD_Hardware_Design

Pre and Post Synthesis Simulation of a Design VSDMemSOC

Language: Verilog - Size: 6.49 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

karim-m-ali/mips-cpu

Simple MIPS 16-bit CPU implemented in VHDL with an assembler in python

Language: VHDL - Size: 491 KB - Last synced at: about 2 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

capopaul/Public-Verilog-Design-Flow-And-Environment

Provide a basic structure to starts a Verilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)

Language: Verilog - Size: 3.91 KB - Last synced at: 10 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

arhamhashmi01/sv-practice

This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language

Language: SystemVerilog - Size: 6.84 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

rohankalbag/multicycle-risc Fork of IITB-RISC-2022/Multicycle_RISC

Course Project - Microprocessors - Spring Semester 2022 - Indian Institute of Technology Bombay

Language: VHDL - Size: 8.85 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

FPGAwars/tool-gtkwave

:seedling: Tool GTKWave for open FPGAs

Size: 1000 Bytes - Last synced at: 13 days ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Bhavan-Naik/16bit_shift_adder

Project to Design and Implement a 16-bit Shift Adder (Serial Adder) using Verilog.

Language: Verilog - Size: 10.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1

siri-n-shetty/Car-Parking-System-iverilog

Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)

Language: Verilog - Size: 1.35 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

vrstanchev/gnu-fpga-exersises

VHDL fpga exersises with Free/FOSS/Libre tools

Language: VHDL - Size: 17.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Tech-mohankrishna/pes_bcdbin

This repository deals with BCD to binary conversion using iverilog as a simulator and yosys as a synthesis tool.

Language: Verilog - Size: 64.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

rohankalbag/superscalar-risc Fork of aweditya/superscalar

Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: VHDL - Size: 6.61 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0