Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Language: VHDL - Size: 25 MB - Last synced at: 8 days ago - Pushed at: 3 months ago - Stars: 212 - Forks: 40

snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

Language: Verilog - Size: 126 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 132 - Forks: 23

michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Language: Verilog - Size: 8.73 MB - Last synced at: 18 days ago - Pushed at: about 3 years ago - Stars: 105 - Forks: 26

adibis/DDR2_Controller

DDR2 memory controller written in Verilog

Language: Verilog - Size: 116 KB - Last synced at: 2 months ago - Pushed at: over 13 years ago - Stars: 78 - Forks: 32

neelkshah/MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Language: Verilog - Size: 138 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 64 - Forks: 13

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Language: Verilog - Size: 1.51 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 62 - Forks: 26

mongrelgem/Verilog-Adders

Implementing Different Adder Structures in Verilog

Language: Verilog - Size: 77.1 KB - Last synced at: 7 months ago - Pushed at: almost 6 years ago - Stars: 60 - Forks: 16

TheSUPERCD/8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Language: Verilog - Size: 173 KB - Last synced at: 5 months ago - Pushed at: over 2 years ago - Stars: 54 - Forks: 15

ashishrana160796/verilog-starter-tutorials 📦

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

Language: Verilog - Size: 25.4 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 34 - Forks: 17

vedic-partap/Computer-Organization-and-Architecture-LAB

Solution to COA LAB Assgn, IIT Kharagpur

Language: Verilog - Size: 1.78 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 34 - Forks: 9

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

Language: JavaScript - Size: 2.07 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 29 - Forks: 7

xiazhuo/nscc2022_personal

NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

Language: VHDL - Size: 33.1 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 28 - Forks: 1

ultraembedded/minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player

Language: Verilog - Size: 595 KB - Last synced at: 6 months ago - Pushed at: almost 6 years ago - Stars: 27 - Forks: 8

mihir8181/VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Language: Verilog - Size: 3.45 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 21 - Forks: 3

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 21 - Forks: 2

pescetti-studio/FliPGA01

FPGA (Verilog) implementation of the Flip01 8-bit processor.

Language: HTML - Size: 1.61 MB - Last synced at: 5 months ago - Pushed at: 8 months ago - Stars: 14 - Forks: 1

NikhilMukraj/spiking-neural-networks-hardware

An FPGA design for simulating biological neurons

Language: SystemVerilog - Size: 437 KB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 14 - Forks: 0

sudhamshu091/Single-Cycle-Risc-Processor-32-bit-Verilog

Single Cycle RISC MIPS Processor

Language: Verilog - Size: 570 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 13 - Forks: 1

RPG-7/HGA101_GPU

Language: Verilog - Size: 38.9 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 13 - Forks: 6

flasonil/Serial-Multiplier

16 bit serial multiplier in SystemVerilog

Language: SystemVerilog - Size: 165 KB - Last synced at: 2 months ago - Pushed at: almost 7 years ago - Stars: 13 - Forks: 5

tongplw/Undertale-Verilog

👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

Language: Verilog - Size: 120 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 12 - Forks: 1

adibis/Interrupt_Controller

An 8 input interrupt controller written in Verilog.

Language: Verilog - Size: 112 KB - Last synced at: over 2 years ago - Pushed at: over 13 years ago - Stars: 12 - Forks: 9

powerplayer9/Voice-Based-Motor-Control

A verilog HDL based project to control a servomotor with voice commands from an android phone.

Language: Verilog - Size: 547 KB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 11 - Forks: 2

Nidhinchandran47/my_rtl_code

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

Language: Verilog - Size: 1.67 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 1

WualFabre/FPGA-Verilog

Practices related to the fundamental level of the programming language Verilog.

Language: Verilog - Size: 5.35 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 10 - Forks: 1

vasanthkumar18/Cache-Compression

Cache compression using BASE-DELTA-IMMEDIATE process in verilog

Language: Verilog - Size: 135 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 10 - Forks: 6

cw1997/SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

Language: HTML - Size: 1.5 MB - Last synced at: 5 months ago - Pushed at: about 3 years ago - Stars: 10 - Forks: 2

aekanshd/booths-multiplier-using-verilog

Language: Verilog - Size: 2.06 MB - Last synced at: 6 months ago - Pushed at: over 6 years ago - Stars: 10 - Forks: 6

RISMicroDevices/RMR8PM3001A

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

Language: C++ - Size: 557 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 9 - Forks: 1

MaorAssayag/Computer-Engineering-Projects

Digital computer structure, Hardware Design Lab & Introduction to Computers for computer engineering projects in C, C#, Assembly, Pspice.

Language: Verilog - Size: 70.4 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 9 - Forks: 3

krutideepanpanda/RISC-V-based-micro-controller-using-OpenLane

This is part of EC383 - Mini Project in VLSI Design.

Language: Verilog - Size: 16.6 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 8 - Forks: 0

tarlaun/CORDIC

Digital System Design Project - Spring 2020

Language: Verilog - Size: 4.24 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 8 - Forks: 0

luk3Sky/Building-A-Processor---Project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

Language: Verilog - Size: 880 KB - Last synced at: 5 months ago - Pushed at: over 6 years ago - Stars: 8 - Forks: 1

LutingWang/FPGA

BUAA Computer Organization Project8 FPGA

Language: Verilog - Size: 10.4 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 8 - Forks: 2

pendkeomkar/SPI

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

Size: 8.96 MB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 8 - Forks: 2

EhsanShahbazii/Digital-VLSI-System-Design-Projects 📦

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

Language: Verilog - Size: 73.2 KB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 0

sudhamshu091/RISC-Pipelined-Processor-32-bit-Verilog

Simple Pipelined 32 bit RISC Processor

Language: Verilog - Size: 195 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 1

Anand270294/AES-encryption-VSLI

EE4415 Project : AES Verilog

Language: Verilog - Size: 15.6 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 7 - Forks: 3

djzenma/2-FPGAs-UART-Protocol

Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.

Language: HTML - Size: 3.8 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 7 - Forks: 0

ErickMaRi/HDL-Bitnet-1.58

Transformer Bitnet en Verilog

Language: Verilog - Size: 4 MB - Last synced at: 2 days ago - Pushed at: about 1 year ago - Stars: 6 - Forks: 1

vSasakiv/RV32I_Processor

Risc-V 32i processor written in the Verilog HDL

Language: Verilog - Size: 6.61 MB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 0

lorentsinani/16bitCPU-Verilog

16 bit CPU created in Vivado with Verilog

Language: Verilog - Size: 20.5 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 6 - Forks: 2

7enTropy7/Artix_7

My experiments with Nexys4 DDR Artix-7 FPGA Board

Language: Verilog - Size: 31.3 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 6 - Forks: 3

MohamedHussein27/SPI_Slave_With_Single_Port_Memory

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with sigle port sync RAM. The project includes the design and code for an SPI Slave, a single-port asynchronous RAM, and an SPI Wrapper that connects the RAM and SPI Slave.

Language: Verilog - Size: 2.18 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 5 - Forks: 0

daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

Language: Verilog - Size: 29.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 5 - Forks: 2

yigitbektasgursoy/Motion_Estimation_Hardware_Verilog

Motion Estimation implementation by using Verilog HDL

Language: Verilog - Size: 2.85 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 5 - Forks: 0

pratikbhuran/Voting_Machine

Voting machine implemented in verilog

Language: Verilog - Size: 146 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1

pa-tiq/vending_machine

Language: Verilog - Size: 8.87 MB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 3

sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

Language: Verilog - Size: 12.6 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 4 - Forks: 2

Vaibhav-Gunthe/Verilog-Projects

A collection of Verilog-based digital design projects, from basic gates to complex modules like ALUs, FSMs, and memory units. Ideal for learning RTL design and synthesis.

Language: Verilog - Size: 2.15 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 4 - Forks: 0

ayush-agarwal-0502/Innovative-Electronic-Door

Digital electronics and verilog project

Language: C - Size: 260 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 0

dutt-arka/Traffic-Light-Control

Intelligent Traffic Light Controller

Language: C++ - Size: 444 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 1

cw1997/graphical_card

a graphical card for displaying text on VGA text mode by D-Sub port

Language: Verilog - Size: 2.61 MB - Last synced at: 5 months ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0

MengmSun/flappybrick

Nexys4FPGA game, verilog, imitate FlappyBird

Language: HTML - Size: 59.9 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 1

aditeyabaral/up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

Language: Verilog - Size: 10.7 KB - Last synced at: 5 months ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 2

mateuspinto/FPGA_Verilog_Ballot_Box-TP2-ISL-UFV

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

Language: Verilog - Size: 10.1 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 1

SaiManojGubbala/RISC-V

A 32 Bit RISC-V Processor Implementation in Verilog

Language: Verilog - Size: 4.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 0

yuri-panchul/tt08-adder-with-flow-control Fork of TinyTapeout/tt08-verilog-template

Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.

Language: SystemVerilog - Size: 43.9 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 3 - Forks: 1

Dhruv0Upadhyay/100_Days_of_RTL

100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog

Language: Verilog - Size: 1.05 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

DopeBiscuit/IEEE-Digital-IC-Design

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

Language: Verilog - Size: 11.5 MB - Last synced at: 5 months ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 1

Daniyar1239/AES-encryption-in-Verilog

AES encryption and decryption algorithms implemented in Verilog programming language

Language: Verilog - Size: 408 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

am2mcu/ATM

An ATM project written in verilog

Language: Verilog - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 0

sudhamshu091/Single-Cycle-Risc-Pipelined-Processor-Verilog

Single Cycle MIPS Pipelined Processor using Verilog

Language: Verilog - Size: 915 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

manikajain11/Traffic-Signal-Controller

Designing and Modelling of an Intelligent Traffic Signal Controller using FSM in Verilog HDL

Language: Verilog - Size: 1.14 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 1

AnoushkaVyas/DRUM

Implementation of DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications in verilog

Language: Python - Size: 3.81 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

sudhamshu091/RISC-Processor-32-bit-Verilog

32 bit RISC Processor

Language: Verilog - Size: 231 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

mircea-pavel-anton/VHDL-Decryption 📦

A small decryption module, written in Verilog, as a university assignment.

Language: Verilog - Size: 557 KB - Last synced at: 8 days ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

varkenvarken/fpga-experiments

Some verilog designs for an icestick40

Language: Verilog - Size: 609 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0

hruskraj/MIPS32-processor

Simple single cycle processor for modified reduced MIPS32 instruction set.

Language: Verilog - Size: 6.84 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0

hansinahuja/32-Bit-ALU

A 32-bit ALU using combinational logic written in Verilog.

Language: C - Size: 8.36 MB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 3 - Forks: 1

kishanpatelec/Distance-measurement

The proposed project is to measure the distance through Ultrasonic sensor which is interfaced with FPGA board.

Language: Verilog - Size: 10.7 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 0

sbaldzenka/xyloni_examples

Examples for Efinix Xyloni FPGA-board.

Language: Verilog - Size: 591 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 1

Jjateen/Snake-Game-Verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

Language: Verilog - Size: 8.63 MB - Last synced at: 5 months ago - Pushed at: 7 months ago - Stars: 2 - Forks: 0

Abhirecket/Square-Shape-Detector

x and y are input signals representing the x and y coordinates, respectively, each being 1-bit wide.

Language: Verilog - Size: 202 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 2 - Forks: 0

MohamedHussein27/RISC-V-Single-Cycle-Implementation

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.

Language: Verilog - Size: 11.4 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 2 - Forks: 0

ANSHVIVEKMALHOTRA/Miniproject-HEATWATCH

HEATWATCH(Temperature monitoring system)-[Digital and System Designs]

Language: Verilog - Size: 39.1 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 2

yigitbektasgursoy/SDRAM_Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

Language: Verilog - Size: 781 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

Lalitgangwar9837/verilog_project

verilog code

Language: Verilog - Size: 97.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

zouaghista/Asynchronous_Fifo_Testbench

A test bench for asynchronous fifos

Language: SystemVerilog - Size: 8.79 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

Precioux/Health-Checking-System

Logic circuits Final Project - Spring 2021

Language: Verilog - Size: 4.06 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

MuballighHossain/VLSI_FSM_Verilog_Simulation

Language: Verilog - Size: 2.96 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 1

skynatepro/MIPS32

Design of 32-bit MIPS Processor

Language: Verilog - Size: 5.7 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

SukhmeetSingh2002/Ecryption-Decryption-System

Encryption Decryption System using Linear Feedback Shift Register

Language: Verilog - Size: 390 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 3

omid-reza/ComputerArchitectureFinalProject 📦

computer architecture course final project

Language: JavaScript - Size: 1.21 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

yvesemmanuel/microwave

second project - Digital System

Language: Verilog - Size: 4.21 MB - Last synced at: 6 months ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 1

yvesemmanuel/introduction_verilog

digital systems

Language: Verilog - Size: 202 KB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0

daniel-saeedi/LogicCircuitDesign 📦

Digital Logic Design Project

Language: Verilog - Size: 48.8 MB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0

mukullokhande99/fifo_hardware_fpga

FIFO implemented on FPGA Spartan 6

Language: Rich Text Format - Size: 21.4 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 1

YajanaRao/Verilog

Verilog Programs

Language: Verilog - Size: 133 KB - Last synced at: 1 day ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

ukashasohail/MIPS_32bit_SCDP_Verilog

An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.

Language: Verilog - Size: 14.6 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

Nish-19/Smart_Lock_System

Deep Learning based Finite State Machine implementation of a Smart Lock System

Language: Python - Size: 17.9 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

GirloftheLimberlost/DigitalLockFPGA

FPGA Digital Lock System with 7 Segment LED Display - Password changeable (Hexadecimal Passwords)

Size: 721 KB - Last synced at: about 1 year ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 2

Saadia-Hassan/Types-of-Verification-Using-SRAM

This repo contains golden vector and randomization testbenches for SRAM module.

Language: Verilog - Size: 7.81 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 2

rootEnginear/CPE223_XO-Game 📦

A tic tac toe game written in Verilog.

Language: Verilog - Size: 8.79 KB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

hansinahuja/Hardware-Based-Teaching-Aid Fork of parasgoyal12/CS203TeachingAid

A hardware-based teaching aid for students to get familiarized with sequential logic using Basys FPGA boards.

Size: 4.04 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

tigerroarm/VerilogDigitalGame

VerilogDigitalGame of HUST.

Language: VHDL - Size: 13.3 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

LutingWang/CPU_pipeplus

BUAA Computer Organization Project7 CPU pipeplus

Language: Verilog - Size: 1.07 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

CasparCheng/Frogger-Game

This is a FPGA digital game using verilog to develop the frogger game

Size: 20.4 MB - Last synced at: about 2 months ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 0

DeepPurohit/Verilog_Projects

Repo for my Verilog Projects

Language: Verilog - Size: 32.2 KB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 0

galihru/logicsim

The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital systems engineering through an intuitive drag-and-drop interface, providin

Language: JavaScript - Size: 423 KB - Last synced at: 2 days ago - Pushed at: 15 days ago - Stars: 1 - Forks: 0