Topic: "verilog-components"
ultraembedded/cores
Various HDL (Verilog) IP Cores
Language: Verilog - Size: 211 KB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 745 - Forks: 218
ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Language: Verilog - Size: 15.1 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 273 - Forks: 43
ZipCPU/dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
Language: C++ - Size: 1.08 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 204 - Forks: 28
TimRudy/ice-chips-verilog
IceChips is a library of all common discrete logic devices in Verilog
Language: Verilog - Size: 1.42 MB - Last synced at: 6 months ago - Pushed at: 7 months ago - Stars: 135 - Forks: 23
Johnlon/spam-1
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
Language: Verilog - Size: 204 MB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 66 - Forks: 8
neelkshah/MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
Language: Verilog - Size: 138 KB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 64 - Forks: 13
wyvernSemi/mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
Language: VHDL - Size: 2.71 MB - Last synced at: 2 months ago - Pushed at: 7 months ago - Stars: 22 - Forks: 3
Wissance/QuickSPI
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Language: Verilog - Size: 127 KB - Last synced at: 2 months ago - Pushed at: over 7 years ago - Stars: 22 - Forks: 7
ZipCPU/wbfmtx
A wishbone controlled FM transmitter hack
Language: Verilog - Size: 197 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 19 - Forks: 1
BrianHGinc/Verilog-Floating-Point-Clock-Divider
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
Language: Verilog - Size: 289 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 14 - Forks: 1
adibis/Interrupt_Controller
An 8 input interrupt controller written in Verilog.
Language: Verilog - Size: 112 KB - Last synced at: about 2 years ago - Pushed at: about 13 years ago - Stars: 12 - Forks: 9
WualFabre/FPGA-Verilog
Practices related to the fundamental level of the programming language Verilog.
Language: Verilog - Size: 5.35 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 10 - Forks: 1
EhsanShahbazii/Digital-VLSI-System-Design-Projects 📦
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
Language: Verilog - Size: 73.2 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 0
IzyaSoft/EasyHDLLib
A coocbook of HDL (primarily Verilog) modules
Language: Verilog - Size: 315 KB - Last synced at: 2 months ago - Pushed at: about 8 years ago - Stars: 6 - Forks: 0
yvesemmanuel/microwave
second project - Digital System
Language: Verilog - Size: 4.21 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 1
yvesemmanuel/introduction_verilog
digital systems
Language: Verilog - Size: 202 KB - Last synced at: 9 days ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0
ferhatozkan/Digital-Logic-Design-Project
University of Marmara, CSE3015 2018 Fall Project
Language: Java - Size: 2.6 MB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0
klsavaj/Computer-Architecture-VerilogCodes-Sheet
Language: HTML - Size: 242 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0
TimRudy/uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
Language: Verilog - Size: 26.7 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
josephkb87/VerilogBasics
Basics of Verilog implementation
Language: SystemVerilog - Size: 19.5 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0
Jamesits/verilog-basic-blocks
数电作业
Language: Verilog - Size: 120 KB - Last synced at: 2 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 1
NotZombieFood/VerilogModules
Verilog modules for reference
Language: C - Size: 9.91 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0
Safa-Taha/Nand2Tetris
Nand2Tetris using Verilog
Language: Verilog - Size: 133 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
shrujan0274/HDLBits-submissions
Solutions for 100+ questions in HDLBits using verilog
Language: Verilog - Size: 37.1 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
fightforit/SystemVerilog-Design-Blocks-Common-Use-Cases-and-Examples
Language: SystemVerilog - Size: 20.5 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
mohanadtalat91/Verilog-HDL
A Verilog HDL code
Language: Verilog - Size: 16.6 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
kivyfreakt/interfaces
Реализация распространенных интерфейсов
Language: Verilog - Size: 5.84 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
verilogcodesarchive/verilogutils
Language: Verilog - Size: 74.2 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
InvincibleJuggernaut/Synthesis
A collection of digital circuits using Verilog.
Language: Verilog - Size: 29.3 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0
