Topic: "rtl"
youngsoft/MyLinearLayout
MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL
Language: Objective-C - Size: 40.3 MB - Last synced at: 3 days ago - Pushed at: about 1 year ago - Stars: 4,419 - Forks: 898
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
Language: Scala - Size: 138 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 4,265 - Forks: 623
chipsalliance/rocket-chip
Rocket Chip Generator
Language: Scala - Size: 20.7 MB - Last synced at: 4 days ago - Pushed at: 30 days ago - Stars: 3,439 - Forks: 1,163
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
Language: C++ - Size: 57.5 MB - Last synced at: about 14 hours ago - Pushed at: about 15 hours ago - Stars: 2,882 - Forks: 664
layoutBox/PinLayout
Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]
Language: Swift - Size: 19.4 MB - Last synced at: 3 days ago - Pushed at: about 1 year ago - Stars: 2,397 - Forks: 144
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Language: Verilog - Size: 703 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1,923 - Forks: 648
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
Language: Scala - Size: 12.2 MB - Last synced at: 3 days ago - Pushed at: 11 days ago - Stars: 1,888 - Forks: 448
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language: Scala - Size: 53.2 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 1,841 - Forks: 705
SpinalHDL/SpinalHDL
Scala based HDL
Language: Scala - Size: 81.2 MB - Last synced at: 3 days ago - Pushed at: 8 days ago - Stars: 1,783 - Forks: 346
stnolting/neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Language: VHDL - Size: 225 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,757 - Forks: 260
MohammadYounes/rtlcss
Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)
Language: JavaScript - Size: 1.01 MB - Last synced at: 3 days ago - Pushed at: 3 months ago - Stars: 1,695 - Forks: 128
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language: Python - Size: 836 MB - Last synced at: 3 days ago - Pushed at: 3 months ago - Stars: 1,480 - Forks: 395
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Language: SystemVerilog - Size: 9.1 MB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 1,256 - Forks: 288
kartik-v/bootstrap-star-rating
A simple yet powerful JQuery star rating plugin with fractional rating support.
Language: JavaScript - Size: 516 KB - Last synced at: 3 days ago - Pushed at: about 2 years ago - Stars: 1,056 - Forks: 398
siliconcompiler/siliconcompiler
Modular hardware build system
Language: Python - Size: 336 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 988 - Forks: 101
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Language: SystemVerilog - Size: 5.49 MB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 904 - Forks: 284
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
Language: SystemVerilog - Size: 17.6 MB - Last synced at: 25 days ago - Pushed at: almost 2 years ago - Stars: 870 - Forks: 227
eldraco/Salamandra
Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.
Language: Python - Size: 16.3 MB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 829 - Forks: 112
AdevintaSpain/Leku
:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.
Language: Kotlin - Size: 13.7 MB - Last synced at: 1 day ago - Pushed at: 8 months ago - Stars: 771 - Forks: 170
open-sdr/openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Language: Verilog - Size: 484 MB - Last synced at: 2 days ago - Pushed at: 10 days ago - Stars: 752 - Forks: 256
ultraembedded/cores
Various HDL (Verilog) IP Cores
Language: Verilog - Size: 211 KB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 745 - Forks: 218
WangXuan95/FPGA-USB-Device
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
Language: Verilog - Size: 494 KB - Last synced at: 25 days ago - Pushed at: 5 months ago - Stars: 722 - Forks: 120
4xmen/Web-Package-RTL
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
Language: HTML - Size: 19.4 MB - Last synced at: about 13 hours ago - Pushed at: 7 months ago - Stars: 664 - Forks: 205
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
Language: Rust - Size: 78.1 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 625 - Forks: 36
seldridge/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Language: Verilog - Size: 72.3 KB - Last synced at: about 2 months ago - Pushed at: about 7 years ago - Stars: 564 - Forks: 140
ucb-bar/riscv-mini 📦
Simple RISC-V 3-stage Pipeline in Chisel
Language: Scala - Size: 1.3 MB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 563 - Forks: 115
fondesa/recycler-view-divider
A library which configures a divider for a RecyclerView.
Language: Kotlin - Size: 1.6 MB - Last synced at: 10 days ago - Pushed at: 11 days ago - Stars: 512 - Forks: 44
01walid/awesome-arabic
A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.
Size: 120 KB - Last synced at: 10 days ago - Pushed at: 8 months ago - Stars: 510 - Forks: 94
MahdiMajidzadeh/bootstrap-v4-rtl
RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
Language: JavaScript - Size: 17.5 MB - Last synced at: 6 days ago - Pushed at: about 1 month ago - Stars: 472 - Forks: 167
The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language: Verilog - Size: 828 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 418 - Forks: 339
Nuand/bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
Language: VHDL - Size: 161 KB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 413 - Forks: 50
pymtl/pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Language: Python - Size: 5.36 MB - Last synced at: 3 days ago - Pushed at: 13 days ago - Stars: 411 - Forks: 50
WangXuan95/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
Language: SystemVerilog - Size: 62.2 MB - Last synced at: 25 days ago - Pushed at: over 1 year ago - Stars: 398 - Forks: 79
rggen/rggen
Code generation tool for control and status registers
Language: Ruby - Size: 510 KB - Last synced at: 6 days ago - Pushed at: 3 months ago - Stars: 381 - Forks: 46
intel/rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
Language: Dart - Size: 18.3 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 369 - Forks: 65
20lives/tailwindcss-rtl
Enabling bidirectional support on tailwindcss framework
Language: JavaScript - Size: 400 KB - Last synced at: about 21 hours ago - Pushed at: over 2 years ago - Stars: 357 - Forks: 32
formwerkjs/formwerk
📝 The Vue.js framework for building tailored, accessible, and high-quality forms.
Language: TypeScript - Size: 1.49 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 349 - Forks: 14
duolingo/rtl-viewpager 📦
ViewPager with RTL support :arrows_counterclockwise:
Language: Java - Size: 2.42 MB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 340 - Forks: 53
t0gre/react-datepicker
An easily internationalizable, accessible, mobile-friendly datepicker library for the web, build with styled-components.
Language: JavaScript - Size: 5.35 MB - Last synced at: 20 days ago - Pushed at: over 1 year ago - Stars: 330 - Forks: 54
erfanmola/DontAskToAsk
⭕️ نپرس که بپرسم، فقط بپرس ⭕️
Language: Vue - Size: 1.59 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 329 - Forks: 11
chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
Language: SystemVerilog - Size: 12.2 MB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 313 - Forks: 79
bitbrain/jekyll-dash
🌒 Light and dark blog theme for Jekyll, inspired by Dash UI for Atom.
Language: SCSS - Size: 3.27 MB - Last synced at: 1 day ago - Pushed at: about 1 year ago - Stars: 307 - Forks: 112
WangXuan95/FPGA-SDcard-Reader
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
Language: Verilog - Size: 168 KB - Last synced at: 25 days ago - Pushed at: over 1 year ago - Stars: 290 - Forks: 66
phphe/he-tree
Highly customizable draggable Vue.js tree component.
Language: TypeScript - Size: 9.27 MB - Last synced at: 8 days ago - Pushed at: about 1 month ago - Stars: 284 - Forks: 35
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Language: SystemVerilog - Size: 820 KB - Last synced at: about 1 month ago - Pushed at: over 5 years ago - Stars: 275 - Forks: 60
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
Language: SystemVerilog - Size: 32.8 MB - Last synced at: 12 days ago - Pushed at: 18 days ago - Stars: 274 - Forks: 82
mortezakarimi/gentelella-rtl
Free RTL Bootstrap 3 Admin Template
Language: HTML - Size: 29.7 MB - Last synced at: 9 days ago - Pushed at: 7 months ago - Stars: 269 - Forks: 73
framevuerk/framevuerk
Fast, Responsive, Multi Language, Both Direction Support and Configurable UI Framework based on Vue.js.
Language: Vue - Size: 7.82 MB - Last synced at: 16 days ago - Pushed at: over 2 years ago - Stars: 264 - Forks: 18
lastweek/fpga_readings
Recipe for FPGA cooking
Language: Verilog - Size: 51.8 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 258 - Forks: 56
RonMelkhior/tailwindcss-dir
Adds direction (LTR, RTL) variants to your Tailwind project
Language: JavaScript - Size: 54.7 KB - Last synced at: 19 days ago - Pushed at: over 4 years ago - Stars: 231 - Forks: 11
wayfair-archive/awesome-learning 📦
Awesome Learning - Learn JavaScript and Front-End Fundamentals at your own pace
Language: JavaScript - Size: 4.45 MB - Last synced at: 12 days ago - Pushed at: over 3 years ago - Stars: 228 - Forks: 90
abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
Language: Verilog - Size: 17 MB - Last synced at: about 1 month ago - Pushed at: 7 months ago - Stars: 221 - Forks: 27
yifaneye/react-gallery-carousel
Carousel component 🎠🎠🎠 supporting touch, mouse, keyboard, thumbnails, fullscreen, lazy loading, SSR and customisations. 👉 Live editor: https://yifanai.com/rgcd1 👉 Example: https://koalaliving.com.au/Arya-Sand-Beige-Vegan-Leather-Dining-Chair
Language: JavaScript - Size: 2.2 MB - Last synced at: 11 days ago - Pushed at: over 1 year ago - Stars: 215 - Forks: 29
Nic30/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Language: Python - Size: 19.1 MB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 209 - Forks: 28
bu-icsg/dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Language: Scala - Size: 1.81 MB - Last synced at: 8 days ago - Pushed at: over 5 years ago - Stars: 209 - Forks: 36
alanorth/hugo-theme-bootstrap4-blog
A blogging-centric Bootstrap v4 theme for the Hugo static site generator.
Language: HTML - Size: 4.26 MB - Last synced at: 2 days ago - Pushed at: about 1 month ago - Stars: 207 - Forks: 134
WangXuan95/FPGA-JPEG-LS-encoder
An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。
Language: Verilog - Size: 4.49 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 199 - Forks: 38
DelphiWorlds/KastriFree 📦
Free version of the Kastri library
Language: Pascal - Size: 122 MB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 194 - Forks: 113
ucb-bar/constellation
A Chisel RTL generator for network-on-chip interconnects
Language: Scala - Size: 1.61 MB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 192 - Forks: 28
airbnb/react-with-direction
Components to provide and consume RTL or LTR direction in React
Language: JavaScript - Size: 47.9 KB - Last synced at: 8 days ago - Pushed at: about 2 years ago - Stars: 190 - Forks: 32
WangXuan95/FPGA-ftdi245fifo
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
Language: Verilog - Size: 250 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 189 - Forks: 59
WangXuan95/FPGA-CAN
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
Language: Verilog - Size: 416 KB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 186 - Forks: 56
stnolting/neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
Language: VHDL - Size: 662 KB - Last synced at: 3 days ago - Pushed at: 4 months ago - Stars: 183 - Forks: 23
lulinchen/cnn_open
A hardware implementation of CNN, written by Verilog and synthesized on FPGA
Language: Coq - Size: 11.6 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 181 - Forks: 69
vkalinichev/postcss-rtl
PostCSS plugin for RTL-adaptivity
Language: JavaScript - Size: 909 KB - Last synced at: 1 day ago - Pushed at: over 2 years ago - Stars: 175 - Forks: 32
openasic-org/xkISP
xkISP：Xinkai ISP IP Core (HLS)
Language: Verilog - Size: 13.4 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 167 - Forks: 83
hdl-modules/hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Language: VHDL - Size: 3.63 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 165 - Forks: 29
WangXuan95/FPGA-FixedPoint
Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
Language: Verilog - Size: 75.2 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 164 - Forks: 28
SpinalHDL/SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
Language: Scala - Size: 1.98 MB - Last synced at: 25 days ago - Pushed at: 2 months ago - Stars: 156 - Forks: 41
ics-jku/wal
WAL enables programmable waveform analysis.
Language: Python - Size: 1.73 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 146 - Forks: 20
renegadevi/nuxt-boilerplate
A ready to use Nuxt 3 boilerplate. (w/ HTTPS, Tailwind, i18n+RTL, Pinia, GDPR, Dark mode, TypeScript, Prettier, ESLint etc.)
Language: Vue - Size: 747 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 143 - Forks: 21
KASIRGA-KIZIL/tekno-kizil
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
Language: Verilog - Size: 1.04 GB - Last synced at: 12 months ago - Pushed at: almost 2 years ago - Stars: 139 - Forks: 11
WangXuan95/FPGA-DDR-SDRAM
An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
Language: Verilog - Size: 437 KB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 129 - Forks: 25
ucsc-vama/essent
high-performance RTL simulator
Language: Scala - Size: 1020 KB - Last synced at: 10 months ago - Pushed at: 11 months ago - Stars: 125 - Forks: 12
zeroxme/bootstrap-3-arabic
bootstrap 3 arabic
Language: JavaScript - Size: 6.4 MB - Last synced at: 9 days ago - Pushed at: over 9 years ago - Stars: 125 - Forks: 72
ahmadajmi/markdown-arabic
Write Markdown in Arabic
Language: JavaScript - Size: 242 KB - Last synced at: 17 days ago - Pushed at: about 8 years ago - Stars: 120 - Forks: 17
elchininet/postcss-rtlcss
PostCSS plugin to automatically build Cascading Style Sheets (CSS) with Left-To-Right (LTR) and Right-To-Left (RTL) rules using RTLCSS
Language: TypeScript - Size: 19.4 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 118 - Forks: 17
Guenael/rtlsdr-wsprd
WSPR daemon for RTL receivers
Language: C - Size: 1.04 MB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 118 - Forks: 29
ilhammeidi/veluxi-starter
Veluxi Vue.js Starter Project with Nuxt JS and Vuetify
Language: SCSS - Size: 5.16 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 112 - Forks: 54
kamilmielnik/scrabble-solver
Free, open-source, cross-platform, multi-language analysis tool for Scrabble, Scrabble Duel, Super Scrabble, Letter League, Literaki, and Kelimelik. Quickly find the top-scoring words using the given board and tiles. Available in 8 languages.
Language: TypeScript - Size: 29.7 MB - Last synced at: about 21 hours ago - Pushed at: 21 days ago - Stars: 111 - Forks: 26
PerseusTheGreat/bootstrap-4-rtl Fork of twbs/bootstrap
Unofficial RTL-ized edition of Bootstrap 4.x
Language: JavaScript - Size: 135 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 109 - Forks: 28
poormonfared/sb-admin2
this is an RTL Version of sb-admin2 Template, one of free template series in startbootstrap.com , (download remain file from startbootstrap.com)
Language: HTML - Size: 956 KB - Last synced at: over 1 year ago - Pushed at: about 10 years ago - Stars: 108 - Forks: 48
DediData/Bootstrap-RTL
Bootstrap RTL Standard 3 and 4
Size: 96.7 KB - Last synced at: about 1 month ago - Pushed at: almost 6 years ago - Stars: 102 - Forks: 25
dhogborg/rtl-gopow
Render tables from rtl_power to a nice heat map
Language: Go - Size: 1.02 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 100 - Forks: 10
blarney-lang/blarney
Haskell library for hardware description
Language: Haskell - Size: 3.79 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 98 - Forks: 11
WangXuan95/FPGA-UART
Include 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。
Language: Verilog - Size: 511 KB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 97 - Forks: 19
WangXuan95/FPGA-SDfake
Imitate SDcard using FPGAs. 使用FPGA模拟和伪装SD卡。
Language: Verilog - Size: 18.3 MB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 94 - Forks: 18
iammituraj/pequeno_riscv
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
Language: SystemVerilog - Size: 3.6 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 91 - Forks: 7
TheYahya/thewhite
:black_nib: It's a minimal and light wordpress blog theme :art:
Language: CSS - Size: 2.76 MB - Last synced at: 1 day ago - Pushed at: over 4 years ago - Stars: 91 - Forks: 14
michaelehab/AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
Language: Verilog - Size: 8.73 MB - Last synced at: 2 months ago - Pushed at: almost 3 years ago - Stars: 90 - Forks: 21
mit-han-lab/spatten
[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
Language: Scala - Size: 1.98 MB - Last synced at: 4 days ago - Pushed at: 9 months ago - Stars: 86 - Forks: 10
PrincetonUniversity/AutoSVA
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
Language: Python - Size: 57 MB - Last synced at: 6 days ago - Pushed at: about 1 year ago - Stars: 83 - Forks: 25
MahdiMajidzadeh/materialize-rtl
RTL version of materializecss framework v1.0.0
Language: JavaScript - Size: 29.3 MB - Last synced at: 6 days ago - Pushed at: over 2 years ago - Stars: 83 - Forks: 47
chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
Language: VHDL - Size: 1.91 GB - Last synced at: about 12 hours ago - Pushed at: 1 day ago - Stars: 81 - Forks: 0
WilsonChen003/HDLGen
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
Language: Verilog - Size: 21.1 MB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 81 - Forks: 21
ilhammeidi/awrora-starter
Landing page template built with one of most popular javascript library Vue.JS, Vuetify (Material Design) and Nuxt.JS with SSR.
Language: Vue - Size: 1.31 MB - Last synced at: 28 days ago - Pushed at: over 1 year ago - Stars: 79 - Forks: 37
RamezIssac/django-tabular-permissions
Display Django permissions in a HTML table that is translatable and easily customized.
Language: Python - Size: 97.7 KB - Last synced at: 5 days ago - Pushed at: about 1 year ago - Stars: 77 - Forks: 14
QueraTeam/mattermost-rtl
Adds RTL support to Mattermost
Language: Go - Size: 2.36 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 73 - Forks: 4
mmdsharifi/CoreUI-Free-Bootstrap-Admin-Template-RTL
👌🏼 CoreUI is free bootstrap admin template. http://coreui.io
Language: HTML - Size: 1.95 MB - Last synced at: about 1 month ago - Pushed at: over 8 years ago - Stars: 73 - Forks: 32
WangXuan95/FPGA-SDcard-Reader-SPI
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。
Language: Verilog - Size: 3.09 MB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 72 - Forks: 17