Topic: "digital-logic"
logisim-evolution/logisim-evolution
Digital logic design tool and simulator
Language: Java - Size: 108 MB - Last synced at: 4 days ago - Pushed at: 7 days ago - Stars: 5,661 - Forks: 718
tilk/digitaljs
Teaching-focused digital circuit simulator
Language: JavaScript - Size: 7.56 MB - Last synced at: 13 days ago - Pushed at: 12 months ago - Stars: 703 - Forks: 54
TimRudy/ice-chips-verilog
IceChips is a library of all common discrete logic devices in Verilog
Language: Verilog - Size: 1.42 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 135 - Forks: 23
AnuragAnalog/GateResources
Here are my GATE CSE 2021 Resources
Size: 45.4 MB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 132 - Forks: 42
matijakevic/mcircuit
A digital logic simulator inspired by Logisim.
Language: Python - Size: 131 KB - Last synced at: 18 days ago - Pushed at: almost 4 years ago - Stars: 48 - Forks: 9
sabertazimi/hust-lab
Labs for Computer Science: C, Assembly, Data Structure, CSAPP, HSI, MATLAB, Digital Logic, Verilog, Compilers, Operating Systems
Language: C - Size: 323 MB - Last synced at: 14 days ago - Pushed at: 5 months ago - Stars: 30 - Forks: 7
Aparnaraha/Gate2024
here the notes provided by the seniors who already cracked IITs as well as how much I'll cover for my exams I'll provide my notes as well. If you want you can access the course by these links also
Size: 1.31 GB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 28 - Forks: 3
2catycm/SUSTech-CS202_214-Computer_Organization-Project
This is the mirror for gitee in github for project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology， which is to manufacture a CPU. 这是南方科技大学CS202/214计算机组成原理课程的大作业——实现一个CPU。
Language: Verilog - Size: 105 MB - Last synced at: about 1 month ago - Pushed at: almost 3 years ago - Stars: 15 - Forks: 0
chaseruskin/legoHDL
An experimental package manager and development tool for Hardware Description Languages (HDL).
Language: Python - Size: 3.9 MB - Last synced at: 8 days ago - Pushed at: about 3 years ago - Stars: 14 - Forks: 2
dramforever/finlog
Compiling finite generators to digital logic. WIP
Language: Haskell - Size: 119 KB - Last synced at: 27 days ago - Pushed at: over 4 years ago - Stars: 14 - Forks: 0
fcayci/vhdl-digital-design
VHDL code examples for a digital design course
Language: VHDL - Size: 114 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 14 - Forks: 5
Es1chUbJyan9/32bit_Quine-McCluskey_and_Petrick_Method_in_C
32bit Simplifier of Boolean functions
Language: C - Size: 66.4 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 14 - Forks: 3
anuejn/XC9500
WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.
Language: Python - Size: 1.6 MB - Last synced at: 13 days ago - Pushed at: over 3 years ago - Stars: 10 - Forks: 3
djcopley/QuineMcCluskey
A powerful tool for minimizing Boolean functions
Language: Python - Size: 282 KB - Last synced at: 6 days ago - Pushed at: 8 months ago - Stars: 9 - Forks: 3
WilliamYi96/SimpleComputer
The design and implementation of simple computer by quartus.
Language: VHDL - Size: 7.62 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 8 - Forks: 1
DheerendraRathor/vhdl
This repository contains the codes for various type of circuits simulated in VHDL in Xilinx ISE Design.
Language: VHDL - Size: 1.59 MB - Last synced at: over 1 year ago - Pushed at: about 11 years ago - Stars: 8 - Forks: 1
bespoyasov/binary-full-adder-in-the-game-of-life
Binary adder implementation in the Game of Life written in JavaScript using canvas.
Language: JavaScript - Size: 199 KB - Last synced at: 19 days ago - Pushed at: 3 months ago - Stars: 6 - Forks: 1
Multimedia-Processing/Digital-Logic-Design
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
Language: Verilog - Size: 181 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 2
tuura/sync-models
Tool for creating synchronous models and behavioral specifications for asynchronous circuits
Language: Verilog - Size: 543 KB - Last synced at: 5 months ago - Pushed at: almost 7 years ago - Stars: 6 - Forks: 0
rohityadav-sas/K-Map-Solver
The Karnaugh Map (KMap) Solver is a C++ application featuring a graphical interface for solving Karnaugh Maps. Users can interactively input values into a KMap grid and calculate corresponding minterms. The project aims to simplify Boolean expressions and visualize them using logic gates.
Language: C++ - Size: 9.52 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 4 - Forks: 1
twlite/digital-logic
A collection of digital logic utilities
Language: TypeScript - Size: 52.7 KB - Last synced at: 1 day ago - Pushed at: about 2 years ago - Stars: 4 - Forks: 1
tdepke2/CircuitSim2
Graphical tool for developing and testing digital logic circuits from the gate level, built with C++ and SFML.
Language: C++ - Size: 32.8 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 3 - Forks: 0
RezaGooner/Karnaugh-Map
The program in GUI that show and minimize with Karnaugh-Map in Python & C++
Language: C++ - Size: 1.59 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 3 - Forks: 0
bryan-hoang/elec-271-digital-systems-labs 📦
VHDL Code for Labs done in a 2nd year engineering Digital Systems course (ELEC 271) at Queen's University.
Language: VHDL - Size: 10.7 KB - Last synced at: about 23 hours ago - Pushed at: 5 months ago - Stars: 3 - Forks: 1
tinsir888/nju-dlco-lecture
My solutions for DLCO(Digital Logic and Computer Organization) lecture assignments of NJU-ProjectN. DLCO is the bridging course for Project YSYX. Each lab eventually runs on NVBoard(another sub-project of NJU-ProjectN), a vitual FPGA.
Language: Makefile - Size: 227 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 0
RyanAlameddine/WireFormSketch
Simulating hand drawn digital-logic circuit diagrams projected onto a sheet of paper!
Language: C# - Size: 222 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0
lxriscute0501/SUSTech-Notes-of-CS
Undergraduate Courses in Computer Science at SUSTech
Language: Java - Size: 358 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 2 - Forks: 0
mcquerol/electronic-systems
Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.
Size: 8.95 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 2 - Forks: 0
Layheng-Hok/Digital-Piano
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
Language: Verilog - Size: 9.97 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 2 - Forks: 1
namberino/nam85
An 8085-based Computer
Language: Verilog - Size: 691 KB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0
lubinpappalardo/digital-logic-sim
Lubin Pappalardo's official Digital Logic Simulator.
Language: JavaScript - Size: 336 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
dakotacookenmaster/ByteWeave
ByteWeave is a web-based application that allows students to simulate digital circuits using a variety of logic gates, including AND, OR, NOT, NAND, NOR, INPUT, OUTPUT, and Seven Segment Displays. Instructors can also create assignments with custom logic circuits that are automatically graded.
Language: TypeScript - Size: 347 KB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
itdevwu/BUPT-digital-logic-lab
北京邮电大学“数字逻辑与数字系统”实验课程的电路接线图。
Size: 44.9 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0
danielkim802/PyLogic
Python digital logic library
Language: Python - Size: 63.5 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 1
techcentaur/UART-Project
Universal Asynchronous Receiver-Transmitter. Semester project of Digital Logic and System Design course of fall 2017, IIT Delhi.
Language: VHDL - Size: 2.86 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0
meetps/EE-214
VHDL and Verilog Codes for Digital Lab.
Language: VHDL - Size: 3.56 MB - Last synced at: 2 months ago - Pushed at: almost 10 years ago - Stars: 2 - Forks: 0
mcquerol/memory-cell-vhdl
VHDL project for a single-bit memory cell. Demonstrates digital logic design.
Language: VHDL - Size: 43.9 KB - Last synced at: 2 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
jack-mil/atpg-toolkit
Fault-free circuit simulation, deductive fault simulation, and PODEM test pattern generation library
Language: Python - Size: 1.83 MB - Last synced at: 19 days ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
Ite-2022-pwr/luc-ultimate
repo for the LaTeX source of the life-saving PDF
Language: TeX - Size: 3.91 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
AlessandroFornara/Digital-Logic-Design-Project-2022-2023 📦
Digital Logic course's final test (Polytechnic of Milan, 2022/23 A.Y.)
Language: VHDL - Size: 2.07 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
etcyl/MLP
A multilayer perceptron that uses an OOP approach towards solving all 16 digital logic functions.
Language: Python - Size: 7.81 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
TimRudy/uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
Language: Verilog - Size: 26.7 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
lingbai-kong/FPGA-lathe-simulation-system
同济大学CS《数字逻辑》大作业: 车床仿真系统TongJi University CS digital logic assignment: lathe simulation system
Language: Verilog - Size: 78.4 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
djzenma/A-Star-Integrated-Circuit-Routing
A Star Algorithm used to route pins using Metal 1, Metal 2 and Metal 3 wires.
Language: Java - Size: 2.27 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0
lukacupic/Hamming-Simulator
A web simulator of binary data transmission using the Hamming code for error detection and correction
Language: JavaScript - Size: 114 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
axelitama/Progetto-Reti-Logiche-2020-2021
Final project of the course Reti Logiche (Digital Logic Design) at Politecnico di Milano
Language: VHDL - Size: 777 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
FranMaric/diglog
Web app that helps you with subject "Digitalna logika" at FER. Check it out!
Language: Dart - Size: 16.1 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0
hansinahuja/Digital-Logic-Design
Codes written by me in my Digital Logic Design course.
Language: HTML - Size: 1 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0
UgurcanAkkok/Navi
A nand2tetris-like Project written entirely in ANSI C
Language: C - Size: 15.6 KB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0
X-czh/FlappyBird 📦
FlappyBird on VGA Display using Verilog
Language: Verilog - Size: 1.14 MB - Last synced at: almost 2 years ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0
zachthearcticfox/tklogicsim
WIP Logic Simulator with the Tkinter library
Language: Python - Size: 21.6 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
hvardhan1437/EOC-ASSIGNMENT-4
Implementation of digital logic circuits for EOC Assignment 4 using HDL-style modules, based on the Nand2Tetris curriculum. Includes gates, multiplexers, demultiplexers, and adders.
Language: MATLAB - Size: 3.91 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0
AlonMell/build-a-computer
Implementation of a modern computer system from first principles. Starting with basic NAND gates and progressively building a CPU
Language: Hack - Size: 61.5 KB - Last synced at: 15 days ago - Pushed at: 19 days ago - Stars: 0 - Forks: 0
5y3b/Tabular-Method
Quine-McCluskey Minimization Technique (Tabular-Method) Digital Logic Design
Language: Python - Size: 5.86 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
prabesh6907/K-Map-Solver Fork of rohityadav-sas/K-Map-Solver
The Karnaugh Map (KMap) Solver is a C++ application featuring a graphical interface for solving Karnaugh Maps. Users can interactively input values into a KMap grid and calculate corresponding minterms. The project aims to simplify Boolean expressions and visualize them using logic gates.
Language: C++ - Size: 9.52 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
Ite-2022-pwr/ITE-IS-Semestr-3
Semestr 3, studia inżynierskie: Języki programowania, LUC, PPS
Size: 1.95 KB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
RhinoDevel/RhinoGator
Digital logic circuit simulator.
Language: C# - Size: 213 KB - Last synced at: about 2 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0
zahi1/Digital-Electronics
Digital Electronics repo includes Boolean algebra and logic circuit design, covering topics such as gates, combinational and sequential circuits. It will help you learn logical circuit design principles, analyze circuits using automated tools, and delve into VHDL coding for the design and implementation of digital circuits on FPGA devices.
Size: 2.42 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Tingwuren/BottlingTablets
数字逻辑课程设计之药片管理系统
Language: VHDL - Size: 4.88 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
lucaszapataEE/BCD_Adder
A project that adds two 4-digit BCD numbers and displays the sum to a 7-segment display.
Size: 5.76 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
anshuljagtap/Computer-Systems-and-Assembly-Language-and-Lab
Introduction to computer systems and assembly language and how computers compute in hardware and software. Topics include digital logic, number systems, data structures, compiling/assembly process, basics of the system software, and computer architecture.
Language: Assembly - Size: 15.4 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
edogenna/Digital-Logic-Project-2023
Digital Logic course's final test (Polytechnic of Milan, 2022/23 A.Y.)
Language: VHDL - Size: 1.41 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
mymermer/Logic_Lab_Homework
All 3 Digital Logic Laboratory Homework
Size: 4.53 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
bislerium/decadder
➕A simple python script to add two numbers by converting them to binaries and applying to a aggregated digital logic of Full adders. Uses AND, OR, XOR gates.
Language: Python - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
DavideTenediniPoliMi/RL_Project_21_22
This was the project assignment for the Digital Logic Design course.
Language: VHDL - Size: 741 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
wani-ham/quine-mccluskey-algorithm
Computational Simulation of Quine-McCluskey Algorithm using C/C++
Language: C++ - Size: 735 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
notkaramel/ECSE222-VHDL
Assignments for ECSE 222 - Digital Logic (F2022)
Language: VHDL - Size: 242 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
nevikw39/LogicDesignLab
EECS207001
Language: Verilog - Size: 14.6 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
saifmohammednipun/digital-logic-design
This course provides an introduction to logic design and basic tools for the design of digital logic systems.
Size: 242 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
amkhrjee/two-bit-alu
A 2-bit ALU made for recreational + academic purposes.
Size: 31.3 KB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
adrielhakiiem/CW1-files
Computer Fundamentals - Coursework 1
Language: Scilab - Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
mauer4/Personal-Project-Verilog-CLOCK
This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques
Language: SystemVerilog - Size: 34.9 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
nevikw39/LogicDesign
11020EECS101002
Language: Verilog - Size: 1.28 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
Ianyourgod/dls-copy
a game heavily inspired off of sebastion lagues digital logic sim
Language: Python - Size: 38.1 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
JoeStrout/pixelLogic
Pixel Logic Circuit Simulator
Language: MAXScript - Size: 230 KB - Last synced at: 12 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
WoolseyWorkshop/Article-Creating-A-Configurable-Multifunction-Logic-Gate-In-Verilog
Creating A Configurable Multifunction Logic Gate In Verilog Article Resources
Language: Verilog - Size: 3.91 KB - Last synced at: 2 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
ILoveBacteria/elevator-state-machine 📦
My Digital Logic course project - Elevator state machine
Language: Verilog - Size: 384 KB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
AylinNaebzadeh/Digital-Logic-Final-Project
This is my final project for digital logic in the third semester of university.
Language: VHDL - Size: 69.3 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
thedhruvrawat/dd
Repository for lab component of the course CS F215: Digital Design at BITS Pilani, Pilani campus (Fall '21)
Size: 6.61 MB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
Ashutosh781/automated-chess
Digital Logic circuit design for an Automated chess.
Size: 9.4 MB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
Enapiuz/logic-circuit-simulator
Logic circuit (based on NAND gates) simulator using OpenCL
Language: C - Size: 18.6 KB - Last synced at: 27 days ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
Enapiuz/logic-board
Logic circuit simulator
Language: TypeScript - Size: 153 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
GirishKhemchandani/Number-System-Calculator
It is very powerful calculator which can convert any number from decimal or binary or octal or hexadecimal to its respective decimal, binary, octal, hexadecimal value. Also it comes with feature of addition, subtraction, multiplication, division of decimal, binary, octal, hexadecimal numbers
Language: HTML - Size: 271 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0
loypt/digitalLogicWithLogisim
digital Logic experiment use Logisim Evolution
Size: 13.7 KB - Last synced at: 12 months ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
GauravJain28/Digital-Clock
Design of a digital clock in VHDL. Course Assignment of COL215: Digital Logic and Systems Design taught in First Sem, 2020-21 at IIT Delhi
Language: VHDL - Size: 3.43 MB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
HaydenGoodfellow/ECE241
Projects from a second-year computer engineering course on digital logic (written in Verilog)
Language: Verilog - Size: 40.3 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
agausmann/wiregrid 📦
A somewhat esoteric digital logic simulator.
Language: Rust - Size: 160 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
HKhademian/SimpleMachine
implementation of a machine executes simple operations in general built-in registers in Verilog
Language: Verilog - Size: 749 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
adamalston/comp411 📦
[sp19] Digital logic, circuit components. Data representation, computer architecture and implementation, assembly language programming.
Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
JackGoldsworth/Digital-Calculator
Digital calculator made with Verilog and Block Diagrams.
Language: Verilog - Size: 16.6 MB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0
ntuifranklin/ENES-246
Language: JavaScript - Size: 3.52 MB - Last synced at: about 1 year ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0
NeilNie/LearnVerilog_Lab1
Learning Verilog, Quartus & FPGA. DA CS 603
Language: Verilog - Size: 18.1 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0
smdsbz/ElevatorController 📦
Digital Logic curriculum design - FPGA-based elevator controller
Language: C - Size: 12.8 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0
hunan-rostomyan/dl-experiments
Computer Design Experiments
Size: 186 KB - Last synced at: about 17 hours ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0
mattesko/ECSE323-Projects
ECSE 323 Labs: FPGA programming and digital systems design experiments
Language: VHDL - Size: 22 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0
SamuelGong/Klotski
A Chinese Klotski game played on Xilinx FPGA
Language: Verilog - Size: 31.3 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0
