Topic: "full-adder"
nxbyte/Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Language: Verilog - Size: 2.23 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 91 - Forks: 21
Elidevin/nandgame.com-solutions
Solutions for NandGame.com
Size: 7.72 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 11 - Forks: 2
luckykadam/adder
Binary Adder using RNN in Keras
Language: Jupyter Notebook - Size: 2.37 MB - Last synced at: 8 days ago - Pushed at: almost 5 years ago - Stars: 9 - Forks: 2
bespoyasov/binary-full-adder-in-the-game-of-life
Binary adder implementation in the Game of Life written in JavaScript using canvas.
Language: JavaScript - Size: 199 KB - Last synced at: 17 days ago - Pushed at: 3 months ago - Stars: 6 - Forks: 1
Zannatul-Naim/Digital-System-Design
Digital System Design Lab Codes using Verilog
Language: Verilog - Size: 52.7 KB - Last synced at: 2 months ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
Keerthiraj-Nagaraj/IBM-quantum-challenge-2020
My solutions to 5 exercises of IBM quantum challenge 2020. Topics include quantum full-adder circuit implementation, circuit optimization and solving various puzzles using Grover's search algorithm.
Language: Jupyter Notebook - Size: 4.62 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
Stavros/Multiplier4bit
A 4bit Multiplier in VHDL
Language: VHDL - Size: 2.94 MB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 1
mcquerol/electronic-systems
Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.
Size: 8.95 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 2 - Forks: 0
DatDarkAlpaca/dat-emulation-sandbox
A simulation where I can connect virtual logic gates and build virtual CIs.
Language: C++ - Size: 60.5 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
Language: Verilog - Size: 102 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2
Nived151/CMOS-DigitalLib
Collection of Digital Library in cadence of 45nm
Size: 948 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 2
jamestiotio/DigiAlpha
Optimized 32-Bit Full Adder, CEC-SAT Verifier & 2-SAT Solver
Language: C++ - Size: 6.96 MB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
imvickykumar999/Logical-Redstone-Reloaded
Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/
Language: Python - Size: 128 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1
jhenals/VHDL-Code---Carry-Select-32bit
Progetto di Elettronica Digitale AA 2022-2023
Size: 4.67 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
aliansgp/VHDL_Adders
Different adders code in VHDL and Comparison
Language: C - Size: 1.3 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
PARSA-MHMDI/design-ALU-with-Xilinx-ISE
This is Amirkabir University Logic Circuit Design final project 2022
Language: C - Size: 8.2 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
rahul21316/verilog-adders
All the various adders in Verilog!
Size: 22.5 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0
jgesc/VerilogTests
A repository for some modules I made while learning Verilog
Language: Verilog - Size: 10.7 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0
hvardhan1437/EOC-ASSIGNMENT-4
Implementation of digital logic circuits for EOC Assignment 4 using HDL-style modules, based on the Nand2Tetris curriculum. Includes gates, multiplexers, demultiplexers, and adders.
Language: MATLAB - Size: 3.91 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
VarshithGovi/Full-Adder-Design-Verilog
Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
Language: Verilog - Size: 11.7 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
afzalamu/8Bit-signed-Full-Adder-on-ARTIX-7-FPGA
Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.
Language: Verilog - Size: 11.7 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
utkarshad21/4-bit-Full-Adder-using-Verilog-HDL
Verilog code and testbench for 4-bit full adder
Language: Verilog - Size: 5.86 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
PoulamiSarkar24/VHDL
This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.
Language: VHDL - Size: 58.6 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
akorkos/digital-electronic-systems
Digital Circuits made with VHDL
Language: VHDL - Size: 2.98 MB - Last synced at: 13 days ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
krish1925/Logic-Design-Verilog
Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module
Language: Tcl - Size: 8.53 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
levyashvin/verilog_codes
basic implementation of logic structures using verilog
Language: Verilog - Size: 17.6 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
CedricRev/simple-calculator-verilog
An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.
Language: Verilog - Size: 24.4 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
JalalSayed1/N-bit-Full-Adder
N-bit Full Adders implementation in VHDL
Language: Tcl - Size: 19.1 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
ginf-ch/digitaltechnik-skript
Skript zur Einführung in die Digitaltechnik
Language: TeX - Size: 12.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
joeymaillette04/VHDL
VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design
Language: VHDL - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
ComboWave/QuantumFullAdder
Implementing Full Adder using QISKIT and IBMQ infrastructure for computation
Language: Jupyter Notebook - Size: 6.84 KB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
bislerium/decadder
➕A simple python script to add two numbers by converting them to binaries and applying to a aggregated digital logic of Full adders. Uses AND, OR, XOR gates.
Language: Python - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
newajsharif91/Verilog_HDL_Digital-System-Design
CSE-2112 Digital Syatem Design LAb
Language: Verilog - Size: 6.84 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
LiamK-Technion/DigSystems_sim1
Digital Systems and Computer Structure, Simulation 1, Spring 2022
Language: SystemVerilog - Size: 1.08 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
archy-co/IC_Testers
Testers for some non elementary integrated circuits: Adder 74283, D Flip-Flop 74174 & Counter 74193 written to be run from PSoC 4
Language: C - Size: 77.1 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
Gabrielgr01/Sumador_ASCII
Sumador de dos números de dos dígitos cada uno codificados en ASCII estándar en 7 bits. Restricción: realizar la suma en binario natural.
Language: Verilog - Size: 5.09 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
scriptographers/CS254-Assignment-3
Assignment 3, Digital Logic Design Lab, Spring 2021, IIT Bombay
Language: VHDL - Size: 1.03 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
gokberkkeptig/Full-Adder
An adder is a digital circuit that performs addition of numbers. Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM.
Language: C - Size: 96.7 KB - Last synced at: 12 months ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
Grv-Singh/Digital-Systems-Design
Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦
Language: MATLAB - Size: 3.24 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
senavs/BitJoy
:heavy_check_mark: Bit, Bytes and Logical Gates Abstraction
Language: Python - Size: 31.3 KB - Last synced at: 6 days ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0
tadakoglu/Full-Adder-in-FPGA
Full adder implementation in Cyclone IV E - EP4CE115F2CBL FPGA
Language: VHDL - Size: 7.81 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0
meysam81/Full-adder-3-bit
from back in the university, a digital design laboratory project adding 2 number of 3 bits
Size: 14.6 KB - Last synced at: about 1 month ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0
