Topic: "adder-subtractor"
gabrielganzer/VHDL-DesignSynthesis
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
Language: Verilog - Size: 7.4 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0
Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
Language: Verilog - Size: 102 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2
yasanthaniroshan/NanoProcessor
A Nanoprocessor designed to run on the Basys3 FPGA desgined using Xlinx Vivado with VHD using Registers, Add/Sub Unit, Decoders, Multiplexers which have been implemented seperately.
Language: JavaScript - Size: 7.2 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1
shreegw/Verilog-Projects
FPGA Projects
Language: Verilog - Size: 175 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
VuxLoc/Digital_Design_With_VHDL
In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.
Size: 1000 Bytes - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
ayeshathoi/DLD-206
Digital Logic Design
Size: 4.69 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
CedricRev/simple-calculator-verilog
An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.
Language: Verilog - Size: 24.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
anthony7586/designing-with-VHDL
porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation
Size: 30.1 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Shakil-RU/Verilog_HDL
"Verilog_HDL" repository contains hardware description language (HDL) code written in Verilog for various digital logic and electronic designs."
Language: Verilog - Size: 87.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
gautamop01/Digital-Systems-and-Design
Learned as a part of CS210 course
Language: VHDL - Size: 16.6 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
