Vedant-02/Verilog-HDL-Lab-Experiments

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

Language: Verilog - Size: 102 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2

aydnzn/Digital-Systems

This repository contains project work for the Digital Systems course. The projects cover fundamental topics of digital design including Boolean algebra, combinational logic, sequential logic, and state machine design

Size: 1.61 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Helogizzy/Somador-BCD8421

Language: VHDL - Size: 121 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0