digital-design | Topic | Ecosyste.ms: Repos

Topic: "digital-design"

baquer/GATE-and-CSE-Resources-for-Students

📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️

Size: 225 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 1,555 - Forks: 411

DrWaleedAYousef/Teaching

Teaching Materials for Dr. Waleed A. Yousef

Language: Mathematica - Size: 157 MB - Last synced at: about 1 month ago - Pushed at: 11 months ago - Stars: 1,004 - Forks: 319

iic-jku/IIC-OSIC-TOOLS Fork of efabless/foss-asic-tools

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Language: Python - Size: 106 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 487 - Forks: 76

thedatabusdotio/fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Language: Verilog - Size: 21.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 103 - Forks: 23

meiniKi/FazyRV

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Language: SystemVerilog - Size: 772 KB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 89 - Forks: 4

medwatt/gmid

Python script for generating lookup tables for the gm/ID design methodology and much more ...

Language: Python - Size: 4.8 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 81 - Forks: 10

bensampson5/libsv

An open source, parameterized SystemVerilog digital hardware IP library

Language: SystemVerilog - Size: 255 KB - Last synced at: 10 days ago - Pushed at: 12 months ago - Stars: 26 - Forks: 4

AdobeAllInOne is a comprehensive suite of creative software tools developed by Adobe. It includes a range of applications for design, photography, video editing, and more, making it the ultimate solution for all your creative needs.

Language: AutoIt - Size: 161 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 24 - Forks: 0

Ghonimo/Pre_Silicon-AHB-to_APB-Verification

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

Language: SystemVerilog - Size: 13.5 MB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 22 - Forks: 6

aditeyabaral/DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

Language: Verilog - Size: 1.82 MB - Last synced at: 2 months ago - Pushed at: about 5 years ago - Stars: 16 - Forks: 9

defano/digital-design

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

Language: Verilog - Size: 35.1 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 14 - Forks: 6

arasgungore/NandGame

Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

Size: 4.85 MB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 14 - Forks: 1

arasgungore/256-colors-with-VGA

A VHDL-based VGA driver to display 256 different colors on a monitor.

Language: VHDL - Size: 492 KB - Last synced at: 2 months ago - Pushed at: almost 3 years ago - Stars: 14 - Forks: 0

chaseruskin/legoHDL

An experimental package manager and development tool for Hardware Description Languages (HDL).

Language: Python - Size: 3.9 MB - Last synced at: about 13 hours ago - Pushed at: about 3 years ago - Stars: 14 - Forks: 2

fcayci/vhdl-digital-design

VHDL code examples for a digital design course

Language: VHDL - Size: 114 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 5

arasgungore/VGA-based-screensaver Fork of aybaras/VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

Language: VHDL - Size: 494 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 12 - Forks: 0

fcayci/sv-digital-design

SystemVerilog examples for a digital design course

Language: SystemVerilog - Size: 29.3 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 9 - Forks: 9

aitesam961/16-Bit-RISC-Core-Processor

A RISC custom-ISA, 16-Bit Processor

Language: Verilog - Size: 22.2 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 8 - Forks: 1

fpgaemu/fpgaemu

Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.

Size: 24.3 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 3

muhammadaldacher/FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7

The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.

Language: VHDL - Size: 56.3 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 8 - Forks: 7

HSD-ESD/VHDL-by-HGB

VHDL-by-HGB is a VS-Code extension for VHDL.

Language: TypeScript - Size: 7.41 MB - Last synced at: 20 days ago - Pushed at: 21 days ago - Stars: 7 - Forks: 0

shahsaumya00/Floating-Point-Adder

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

Language: Verilog - Size: 30.3 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 3

Anand270294/AES-encryption-VSLI

EE4415 Project : AES Verilog

Language: Verilog - Size: 15.6 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 7 - Forks: 3

LunaQu4kez/CS207_23F_Project_GenshinKitchen

2023 Fall CS207 Digital Design Course Project with 120/100 (Full Score)

Language: VHDL - Size: 88.6 MB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 0

aybaras/VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

Language: VHDL - Size: 494 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 2

gabrielganzer/DLX-Microprocessor

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

Language: Verilog - Size: 88.7 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 6 - Forks: 0

player400/pi

My very own CPU architecture! Emulator availible!

Language: C++ - Size: 391 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 5 - Forks: 0

MohamedHussein27/SPI_Slave_With_Single_Port_Memory

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with sigle port sync RAM. The project includes the design and code for an SPI Slave, a single-port asynchronous RAM, and an SPI Wrapper that connects the RAM and SPI Slave.

Language: Verilog - Size: 2.18 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 5 - Forks: 0

meiniKi/RV32I_SC_Logisim

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

Language: Verilog - Size: 707 KB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 5 - Forks: 0

Certseeds/CS207_Digital_Design 📦

SUSTech CS207 Digital Design 2018Fall Materials.

Language: Verilog - Size: 15.1 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 0

MIPT-ILab/digital-design 📦

Lectures on Digital Design

Size: 24.8 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 2

kara-abdelaziz/SEP-CPU

SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU

Language: Assembly - Size: 201 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 1

CapTen101/CircuitVerseDocs Fork of CircuitVerse/CircuitVerseDocs

This is Official CircuitVerse Online Documentation

Size: 34.3 MB - Last synced at: about 1 year ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 0

AliOsm/4x4-karnaugh-map-solver

4 by 4 Karnaugh map solver

Language: C++ - Size: 5.86 KB - Last synced at: 4 days ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 1

gholomia/Fusion

Crawling deep into the world of hardware description language, VHDL. My coursework for the digital design of computer systems course by Dr. M. Saheb Zamani.

Language: JavaScript - Size: 90.6 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 5 - Forks: 0

JoelRomero97/Sistemas-Digitales

Implementaciones para diseño de sistemas digitales, comenzando por Flip Flops, registros, autómatas (Máquinas de Moore y Máquinas de Mealy), memorias ROM y sensores de presencia, utilizando para cada uno de estos, distintos contadores (anillo, década, etc).

Language: VHDL - Size: 4.22 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 5 - Forks: 1

Luca-Dalmasso/DLX

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

Language: Verilog - Size: 16.3 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 1

ZeyadTarekk/Serial-Peripheral-Interface Fork of Abd-ELrahmanHamza/Serial-Peripheral-Interface

Design and implement the following components of the SPI modules using verilog such that they match the requirements of the development testbench and match the SPI specifications: Master Slave Self-Checking Testbenches for the Master and Slave

Language: Verilog - Size: 1.58 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 0

gabrielganzer/VHDL-DesignSynthesis

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

Language: Verilog - Size: 7.4 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0

aditeyabaral/up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

Language: Verilog - Size: 10.7 KB - Last synced at: 2 months ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 2

lstolcman/bachelor-thesis

Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract

Language: Verilog - Size: 228 MB - Last synced at: 3 days ago - Pushed at: almost 7 years ago - Stars: 4 - Forks: 1

Vaibhav-Gunthe/Verilog-Projects

A collection of Verilog-based digital design projects, from basic gates to complex modules like ALUs, FSMs, and memory units. Ideal for learning RTL design and synthesis.

Language: Verilog - Size: 1020 KB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 3 - Forks: 0

HSD-ESD/HDLRegression-by-HGB

HdlRegression-by-HGB is a VS-Code Extension which enables the testexplorer for HDLRegression projects.

Language: TypeScript - Size: 278 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 3 - Forks: 0

HSD-ESD/VUnit-by-HGB

VUnit-by-HGB is a VS-Code extension which enables the testexplorer for VUnit projects.

Language: TypeScript - Size: 1.14 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 1

Werni2A/Valhalla-II

Open-Source VHDL Synthesis for Alhambra II FPGA Board

Language: VHDL - Size: 22.5 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 2

Abdulrahman-Mostafa10/Synopsys-Chip-Design

Language: Verilog - Size: 8.54 MB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 1

mildsunrise/bdf2tikz

🖋 Typeset Quartus II schematics using TikZ (LaTeX)

Language: Python - Size: 45.9 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

mildsunrise/vwf2tikz

🖋 Typeset Quartus II waveform files using TikZ (LaTeX)

Language: Python - Size: 30.3 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

ArvinDelavari/Digital-Circuits-Verilog

Sample Verilog codes for digital circuits

Language: HTML - Size: 9.31 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

hosseinfani/digital_odyssey

Materials for the Computer Science course, Digital Design (Logic Circuits)

Language: C++ - Size: 393 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 4

segocago/CS223-Digital-Design-Highway-Racing

Term project for CS223 Digital - Design course.

Language: SystemVerilog - Size: 384 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 3

urbanij/DDFS

Direct digital frequency synthesizer in Verilog and VHDL.

Language: VHDL - Size: 9.56 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 2

robodhruv/digital-design

VHDL Code Dump for Digital Circuits Lab (EE214), Spring 2017

Language: VHDL - Size: 81.5 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 2

JuanCantu1/VLSI-Projects

CMOS digital circuits implemented at the transistor level with schematic, layout, waveform simulation, and LVS verification, from basic logic gates to an 8-bit ripple-carry adder.

Size: 3.66 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 2 - Forks: 0

JuanCantu1/Interactive-Memory-Game

Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

Language: Verilog - Size: 22.6 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 2 - Forks: 0

joejo-joestar/uni-codes

🐢

Language: C - Size: 17.4 MB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 2 - Forks: 1

RezaGooner/Logic-circuit-Verilog

Language: Verilog - Size: 5.86 KB - Last synced at: 2 months ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

MohamedHussein27/RISC-V-Single-Cycle-Implementation

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.

Language: Verilog - Size: 11.4 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

hossam7amdy/computer-science-major

keep and track my computer science learning journey.

Language: C++ - Size: 122 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

HarieshAnbalagan/RV32I

Minimalistic RV32I RISC-V Processor in System Verilog

Language: SystemVerilog - Size: 392 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

maehw/wokwi-lookup-table-generator

Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates

Language: Python - Size: 61.5 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 1

Khalidmamdou7/floating-point-unit

Single and double precision floating point unit implemented using Verilog HDL

Language: Verilog - Size: 909 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

JoseDavidSS/TDD.Single-Cycle_Processor

Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.

Language: SystemVerilog - Size: 576 KB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

kara-abdelaziz/Simple-VGA-card

A hardware implementation on Logisim of the World's Worst Video Card designed by Ben Eater.

Language: TeX - Size: 476 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

0xcabrex/LT-Spice

Simple Script to install LT Spice on a linux machine

Language: Shell - Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

ZeyadTarekk/ALU Fork of Abd-ELrahmanHamza/ALU

Design and implementation an arithmetic unit that is capable of adding, subtracting and multiplying two signed magnitude numbers, and displays the result of the operation performed along with some additional flags regarding the operation and the result using Logisim.

Size: 1.29 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

hasancaslan/ELEC204-VHDLWashingMachineController

Washing Machine Controller Design Using VHDL.

Language: HTML - Size: 817 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0

ZeyadTarekk/Combinational-Multiplier

Combinational Multiplier Using verilog

Language: Verilog - Size: 826 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0

Saadia-Hassan/Simulation-of-Memristor-Based-Full-Adder

LTSpice simulation software is used to study the behavior of a Memristor. Different logic gates like NOR, NAND and XOR were modelled and simulated followed by the simulation of a memristor based full-adder.

Language: AGS Script - Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 1