GitHub / shahsaumya00 / Floating-Point-Adder

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

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PURL: pkg:github/shahsaumya00/Floating-Point-Adder

Stars: 7
Forks: 3
Open issues: 0

License: mit
Language: Verilog
Size: 30.3 KB
Dependencies parsed at: Pending

Created at: almost 5 years ago
Updated at: over 2 years ago
Pushed at: almost 5 years ago
Last synced at: over 2 years ago

Topics: digital-design, ieee754, pipeline-framework, verilog

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