olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.08 MB - Last synced at: 25 days ago - Pushed at: about 1 month ago - Stars: 687 - Forks: 201

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced at: 10 days ago - Pushed at: about 1 year ago - Stars: 349 - Forks: 83

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.28 MB - Last synced at: about 20 hours ago - Pushed at: about 21 hours ago - Stars: 324 - Forks: 81

stnolting/neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Language: VHDL - Size: 318 KB - Last synced at: 13 days ago - Pushed at: 14 days ago - Stars: 89 - Forks: 19

scarv/xcrypto

XCrypto: a cryptographic ISE for RISC-V

Language: Verilog - Size: 2.03 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 81 - Forks: 10

dpretet/svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Language: Python - Size: 755 KB - Last synced at: 26 days ago - Pushed at: 8 months ago - Stars: 78 - Forks: 17

unixb0y/SystemVerilogSHA256

SHA256 in (System-) Verilog / Open Source FPGA Miner

Language: SystemVerilog - Size: 148 KB - Last synced at: 2 months ago - Pushed at: over 7 years ago - Stars: 78 - Forks: 26

sgherbst/svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Language: SystemVerilog - Size: 253 KB - Last synced at: about 17 hours ago - Pushed at: over 4 years ago - Stars: 44 - Forks: 9

albertxie/iverilog-tutorial

Quickstart guide on Icarus Verilog.

Language: Verilog - Size: 119 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 32 - Forks: 9

yasnakateb/PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

Language: Verilog - Size: 55.7 KB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 19 - Forks: 3

sifferman/fusesoc_template

Example of how to get started with olofk/fusesoc.

Language: Python - Size: 10.7 KB - Last synced at: 3 days ago - Pushed at: almost 4 years ago - Stars: 17 - Forks: 0

aditeyabaral/DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

Language: Verilog - Size: 1.82 MB - Last synced at: 3 months ago - Pushed at: about 5 years ago - Stars: 16 - Forks: 9

Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

Language: Java - Size: 3.39 MB - Last synced at: 7 months ago - Pushed at: over 7 years ago - Stars: 15 - Forks: 1

addisonElliott/SCIC

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

Language: Verilog - Size: 3.52 MB - Last synced at: 3 months ago - Pushed at: over 6 years ago - Stars: 14 - Forks: 1

TheOneKevin/icarusext

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

Language: TypeScript - Size: 586 KB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 11 - Forks: 3

yasnakateb/NoCRouter

👶🏻 My first baby steps into the world of NoC

Language: Verilog - Size: 269 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 11 - Forks: 2

FPGAwars/toolchain-iverilog 📦

:seedling: Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS

Language: Verilog - Size: 58.6 KB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 9 - Forks: 6

esynr3z/pyhdlsim

Example of Python and PyTest powered workflow for a HDL simulation

Language: Python - Size: 11.7 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 9 - Forks: 1

SymbiFlow/XilinxUnisimLibrary Fork of Xilinx/XilinxUnisimLibrary

Apache 2.0 licensed copy of the Xilinx Unisim library.

Language: Verilog - Size: 1.9 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 1

msinger/dmg-sim

SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip

Language: SystemVerilog - Size: 481 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 6 - Forks: 1

GLADICOS/UART

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

Language: Verilog - Size: 352 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 1

librecores/docker-tools

Just a set of Dockerfiles and tools for FuseSoC

Language: Dockerfile - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 5

esynr3z/playhdl

🪀 Tool to play with HDL (inspired by EdaPlayground)

Language: Python - Size: 27.3 KB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1

yasnakateb/PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 75.2 KB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 0

varkenvarken/robin

SoC design targeted at the IceBreaker board

Language: Assembly - Size: 7.32 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 5 - Forks: 0

yasnakateb/WMController

✨🐾✨ A Control System for Washing Machine in Verilog HDL

Language: Verilog - Size: 242 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 1

yasnakateb/UARTCommunication

☎️ UART Communication Implementation in Verilog HDL

Language: Verilog - Size: 4.88 KB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0

aditeyabaral/up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

Language: Verilog - Size: 10.7 KB - Last synced at: 3 months ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 2

jchabloz/verisocks

A generic verification interface to Verilog simulators using TCP sockets

Language: C - Size: 712 KB - Last synced at: 4 days ago - Pushed at: about 1 month ago - Stars: 3 - Forks: 0

RDSik/verilog-transceiver

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

Language: Verilog - Size: 636 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0

fopelite/VerilogGuides

Guides on how to install a SystemVerilog toolchain on different operating systems

Language: Shell - Size: 88.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 2

GLADICOS/SPACEWIRESYSTEMC

This is a test suit spacewire using a model on systemC with a verilog with graphical interface

Language: PHP - Size: 650 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1

yasnakateb/AES

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

Language: Verilog - Size: 32.2 KB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0

yasnakateb/FIFOMemory

📍 A FIFO Memory Implementation in Verilog HDL

Language: Verilog - Size: 128 KB - Last synced at: 3 months ago - Pushed at: almost 6 years ago - Stars: 3 - Forks: 0

brown9804/Verilog-CircuitDesigns-Hub

Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.

Language: Verilog - Size: 4.76 MB - Last synced at: 5 days ago - Pushed at: 14 days ago - Stars: 2 - Forks: 0

stnolting/icarus-verilog-prebuilt 📦

📦 Prebuilt Icarus Verilog simulator package for x64 Linux.

Size: 31.3 KB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

Essenceia/MoldUPD64

RTL implementation of a MoldUPD64 receiver.

Language: Verilog - Size: 2.68 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

sifferman/fusesoc_project_template

A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

Language: Makefile - Size: 4.88 KB - Last synced at: 3 days ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

RomeoMe5/HopfieldFPGA

Implementation of Hopfield network using Verilog

Language: Verilog - Size: 1.26 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

conneroisu/steroscopic-hardware

Steroscopic Depth Map in HW

Language: JavaScript - Size: 23.2 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

Varunkumar0610/RISC-V-32I-5-stage-Pipeline-Core

Implementation of 5 Stage 32I RISC V Pipeline Processor.

Language: Verilog - Size: 1.44 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

Alfredosavi/tangnano-hello

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

Language: Makefile - Size: 8.79 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 1

Ammar-Bin-Amir/Verilog_Practice

Practice Codes of Verilog Language

Language: Verilog - Size: 1.4 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Shreesh-Kulkarni/Hardware-Modelling-Verilog

All basic to advanced hardware models which are used in VLSI Frontend Design using Verilog HDL

Language: Verilog - Size: 153 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

VishalS-HK/DDCO-Lab-UE21CS251A

A Repo that contains the source code for Digital Design and Computer Organisation course.

Language: Verilog - Size: 11.7 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

melchisedech333/verilog-experiments

:space_invader: My studies with Verilog and notions of digital systems.

Language: Verilog - Size: 391 KB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

yasnakateb/SdramController

🛠 A SDRAM controller in Verilog HDL

Language: Verilog - Size: 47.9 KB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

ParimalaS27/Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.

Language: Verilog - Size: 497 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 2

Myaats/chip8

chip8 verilog implementation targeting the terasic de0-nano dev kit

Language: Verilog - Size: 91.8 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

yasnakateb/TrafficLightController

🚦 A digital controller to control traffic in Verilog HDL

Language: Verilog - Size: 85 KB - Last synced at: 3 months ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 1

grant-cox/pinkyfloat

16 bit IEEE floating point implementation or the UK PinKY pipelined processsor architecture.

Size: 640 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

VarshithGovi/Half-Subtractor-Design-Verilog

Gate-level implementation of a half-subtractor using Verilog, featuring a comprehensive testbench, truth table validation, and waveform analysis for beginners in digital design.

Language: Verilog - Size: 20.5 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

VarshithGovi/2bit-Ripple-Carry-Adder-Verilog

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

Language: Verilog - Size: 25.4 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

VarshithGovi/Full-Adder-Design-Verilog

Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

Language: Verilog - Size: 11.7 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

VarshithGovi/2-to-1-Multiplexer-Design-Verilog

Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

Language: Verilog - Size: 17.6 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

arjun-mec/Digital-Combination-Lock

Verilog Implementation of a Digital Combinational Lock which unlocks when a specific 3 bit sequence is entered.

Language: Verilog - Size: 134 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

watbulb/tt-toolchain-build

A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)

Language: Shell - Size: 60.5 KB - Last synced at: 3 days ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

RichaSavant/Icarus-Verilog-HDL-Logical-Circuits-2023

This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.

Language: Verilog - Size: 76.2 KB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Kyrithdagon/EE-CS120A

Language: SystemVerilog - Size: 2.21 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

Language: Verilog - Size: 1.95 KB - Last synced at: about 8 hours ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

mercury-5/Verilog-HDL

Some basic hardware and logic designs and their respective testbenches written in Verilog HDL

Language: Verilog - Size: 18.6 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

LastRagnarokkr/mips16-iverilog

A processor implementation in Icarus Verilog (iVerilog), 16bit MIPS format.

Language: Verilog - Size: 25.4 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

paranlee/guarded_unsigned_counter

Counter with two guardians who count each bit either even or odd.

Language: Verilog - Size: 19.5 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

usman1515/Matrix-Multiplier

Language: SystemVerilog - Size: 38.1 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

nihal-ramaswamy/DDCO-project

A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.

Language: Verilog - Size: 524 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

ImanHosseini/SSegEmu

Emulating a seven-segment display for Verilog debugging purposes.

Language: Java - Size: 929 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

vballoli/mips-processor

Un-pipelined partial MIPS processor implementation in Verilog

Language: Verilog - Size: 6.84 KB - Last synced at: 3 months ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

abhilash-neog/Verilog-Programming

Verilog Lab work at BITS Pilani

Language: Verilog - Size: 3.2 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0