Topic: "netgen"
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language: Python - Size: 836 MB - Last synced at: 5 days ago - Pushed at: 2 months ago - Stars: 1,476 - Forks: 394
VLSIDA/OpenRAM
An open-source static random access memory (SRAM) compiler.
Language: Python - Size: 72 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 886 - Forks: 218
iic-jku/osic-multitool
JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
Language: Verilog - Size: 122 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 58 - Forks: 16
SiavashMT/OCT-MPS
Massively Parallel Simulator of Optical Coherence Tomography (OCT-MPS)
Language: Cuda - Size: 3.8 MB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 23 - Forks: 8
sgherbst/sky130-hello-world
Minimal SKY130 example with self-checking LVS, DRC, and PEX
Language: Shell - Size: 48.8 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 19 - Forks: 9
vsdip/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).
Language: Coq - Size: 13.1 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 1
netgen/NetgenEnhancedBinaryFileBundle
Netgen Enhanced Binary FIle Bundle is an eZ Platform bundle that provides a field type that reimplements ezbinaryfile field type.
Language: PHP - Size: 93.8 KB - Last synced at: 30 days ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 2
adam-rumpf/pynetgen
A Python module for generating random network flows problem instances in DIMACS graph format.
Language: Python - Size: 102 KB - Last synced at: about 20 hours ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
efabless/sak-deprecated
SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
Language: Python - Size: 4.07 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 2
3x10e8/fossi_cochlea Fork of efabless/caravel_user_project
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
Language: Verilog - Size: 211 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 2
dfritschy/ezplatform-gatsby 📦
A simple study showing eZ Platform content consumed by Gatsby via GraphQL
Language: CSS - Size: 379 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0
watbulb/tt-toolchain-build
A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)
Language: Shell - Size: 60.5 KB - Last synced at: 5 days ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0
netgen/ibexa-scheduled-visibility
Content visibility scheduling for Ibexa CMS
Language: PHP - Size: 140 KB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0
the-pinbo/EC302-VLSI-Design-Lab
EC302-VLSI-Design-Lab
Language: Roff - Size: 4.3 MB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
vadim-z/lua-femtk
Lua modules to work with FEA data
Language: Lua - Size: 253 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0
tpaviot/netgen-conda
Conda build for netgen mesher
Language: C++ - Size: 2.86 MB - Last synced at: about 2 months ago - Pushed at: about 8 years ago - Stars: 0 - Forks: 0
