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Topic: "qflow"

aidangoettsch/asg

An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.

Language: Python - Size: 505 KB - Last synced at: about 21 hours ago - Pushed at: over 4 years ago - Stars: 23 - Forks: 4

efabless/ravenna

32-bit RISC-V microcontroller

Language: C - Size: 2.14 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 11 - Forks: 6

vsdip/vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

Language: Coq - Size: 13.1 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 1

brown9804/Designs_Verification

Here you can find different verifications, time analysis, etc.

Language: Verilog - Size: 5.52 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

Pratim-Senapati/qflow-projects

A complete setup for Qflow, an open-source digital VLSI design flow. This repo provides pre-configured example projects, automated installation scripts, and step-by-step instructions to synthesize, place, and route Verilog designs into GDSII layouts. Supports both running example designs and using your own Verilog.

Language: Python - Size: 7.85 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

Yellowflash-070/Oven-FSM-RTL-to-GDS-II-design-using-Qflow

RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.

Language: Verilog - Size: 22.5 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

majabojarska/verilog-prefix-adder

6-bit prefix adder implemented via Verilog HDL.

Language: Verilog - Size: 13.5 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0

Related Topics
verilog 3 graywolf 2 magic 2 yosys 2 open 1 risc-v 1 riscv 1 source 1 vlsi 1 vlsi-design 1 asicflow 1 fsm 1 open-source 1 rtltogds2 1 xilinx-vivado 1 eda 1 eeschema 1 schematics 1 digital-vlsi 1 gdsii-flow 1 magic-vlsi 1 netgen-layouts 1 verilog-project 1 vlsi-automation 1 blifffanout 1 netgen 1 opensource 1 opensta 1 opentimer 1 physicaldesign 1 programmer 1 qrouter 1 rtl 1 scripting-language 1 semiconductor 1 sta 1 static 1 synthesis 1 tcl 1 vsdip 1 prefix-adder 1 analysis 1 aspects 1 designs-verification 1