Topic: "openroad"
google/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Language: Python - Size: 4.08 MB - Last synced at: 14 days ago - Pushed at: 7 months ago - Stars: 3,154 - Forks: 413
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Language: Verilog - Size: 711 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1,960 - Forks: 654
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language: Python - Size: 836 MB - Last synced at: about 24 hours ago - Pushed at: 3 months ago - Stars: 1,495 - Forks: 395
The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language: Verilog - Size: 825 MB - Last synced at: about 15 hours ago - Pushed at: 1 day ago - Stars: 435 - Forks: 349
google/gf180mcu-pdk
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
Language: Makefile - Size: 51.3 MB - Last synced at: 24 days ago - Pushed at: about 2 years ago - Stars: 394 - Forks: 58
efabless/caravel
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
Language: Verilog - Size: 14 GB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 319 - Forks: 82
efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
Language: Python - Size: 31.4 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 272 - Forks: 54
efabless/caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Language: Verilog - Size: 3.61 GB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 135 - Forks: 136
google/open-source-pdks
Index of the fully open source process design kits (PDKs) maintained by Google.
Size: 65.4 KB - Last synced at: 18 days ago - Pushed at: over 2 years ago - Stars: 95 - Forks: 8
google/globalfoundries-pdk-libs-gf180mcu_fd_pr
Primitives for GF180MCU provided by GlobalFoundries.
Language: Python - Size: 214 MB - Last synced at: 7 days ago - Pushed at: almost 2 years ago - Stars: 49 - Forks: 29
daquintero/piel
Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.
Language: Python - Size: 59.8 MB - Last synced at: 1 day ago - Pushed at: about 1 month ago - Stars: 48 - Forks: 8
google/skywater-pdk-libs-sky130_fd_pr_reram
SKY130 ReRAM and examples (SkyWater Provided)
Size: 3.48 MB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 38 - Forks: 8
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
7 track standard cells for GF180MCU provided by GlobalFoundries.
Language: Verilog - Size: 127 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 26 - Forks: 10
google/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram
SRAM macros created for the GF180MCU provided by GlobalFoundries.
Language: Verilog - Size: 1.73 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 17 - Forks: 5
google/skywater-pdk-libs-sky130_fd_sc_hd 📦
"High density" digital standard cells for SKY130 provided by SkyWater.
Language: Verilog - Size: 207 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 16 - Forks: 34
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
9 track standard cells for GF180MCU provided by GlobalFoundries.
Language: Verilog - Size: 125 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 16 - Forks: 11
The-OpenROAD-Project/ORAssistant
OpenROAD's Chatbot Assistant
Language: Python - Size: 16.4 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 15 - Forks: 10
google/globalfoundries-pdk-libs-gf180mcu_fd_io
IO and periphery cells for the GF180MCU provided by GlobalFoundries.
Language: Verilog - Size: 4.84 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 13 - Forks: 7
The-OpenROAD-Project/OpenROAD-Cloud
The source code that empowers OpenROAD Cloud
Size: 2.8 MB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 12 - Forks: 7
google/globalfoundries-pdk-libs-gf180mcu_fd_bd_sram
SRAM build space for the GF180MCU provided by GlobalFoundries.
Size: 8.79 KB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 10 - Forks: 0
nishit0072e/RTL-to-GDSII
Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation
Language: C++ - Size: 7.85 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 7 - Forks: 0
google/globalfoundries-pdk-libs-gf180mcu_osu_sc
Digital standard cells for GF180MCU provided by Oklahoma State University.
Size: 8.79 KB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 7 - Forks: 2
aasthadave9/Advanced-Physical-Design-Using-OpenLANE-Sky130
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
Size: 467 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 7 - Forks: 6
google/skywater-pdk-libs-sky130_fd_sc_hdll 📦
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
Language: Verilog - Size: 213 MB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 6
google/skywater-pdk-libs-sky130_fd_sc_lp 📦
"Low power" digital standard cells for SKY130 provided by SkyWater.
Language: Verilog - Size: 931 MB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 6
google/skywater-pdk-libs-sky90fd_fd_sc 📦
Standard cells for SKY90FD provided by SkyWater.
Size: 7.81 KB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 0
google/skywater-pdk-libs-sky130_fd_sc_hs 📦
"High speed" digital standard cells for SKY130 provided by SkyWater.
Language: Verilog - Size: 1.12 GB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 5
google/skywater-pdk-libs-sky130_fd_sc_ls 📦
"Low speed" digital standard cells for SKY130 provided by SkyWater.
Language: Verilog - Size: 1.16 GB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 5
google/skywater-pdk-libs-sky130_fd_sc_ms 📦
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
Language: Verilog - Size: 920 MB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 5
The-OpenROAD-Project/EDAAC Fork of EDAAC/EDAAC
EDA Analytics Central
Language: Python - Size: 214 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 4
google/skywater-pdk-libs-sky90fd_osu_sc
Standard cells for SKY90FD provided by Oklahoma State University.
Size: 8.79 KB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 0
google/skywater-pdk-libs-sky130_fd_sc_hvl 📦
"High voltage" digital standard cells for SKY130 provided by SkyWater.
Language: Verilog - Size: 72 MB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 5
meeeeet/RTL-to-GDS-Implementation-of-SerDes
Language: Verilog - Size: 4.91 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 1
wokwi/openroad-docker
OpenROAD docker image (with GUI enabled)
Language: Dockerfile - Size: 2.93 KB - Last synced at: 7 days ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 2
efabless/sak-deprecated
SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
Language: Python - Size: 4.07 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 2
abdelrahmanhosny/FlowRunnerAESExample
Running OpenROAD cloud flow on AES design
Language: Verilog - Size: 75.2 KB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 2
Bynaryman/SUF
SUF is a SUperset Framework for OpenROAD that acts as an enhancement graft by augmenting the original capabilities.
Language: Python - Size: 128 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
abdelazeem201/OpenLane Fork of The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Size: 833 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
dade145/Power-analysis-approx-computing
"DSDM2" project @ Politecnico di Milano // AY 2019-2020
Language: Tcl - Size: 546 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 1
nishit0072e/openlane-flow
Openlane is a complete RTL-to-GDS flow, which uses openroad for floorplan, placement etc.
Language: Jupyter Notebook - Size: 2.89 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
watbulb/tt-toolchain-build
A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)
Language: Shell - Size: 60.5 KB - Last synced at: about 13 hours ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0
watbulb/tt-gds-macro-testing
TinyTapeout GDS blackbox macro testing
Language: Python - Size: 186 KB - Last synced at: about 13 hours ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
Pa1mantri/VSDMemSOC
VSDMemSOC Implementation flow:: RTL2GDSII
Language: Verilog - Size: 1.52 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
rahulearn2019/msvsdpim
Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.
Language: Python - Size: 3.77 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 2
Swagatika-Meher/msvsd2bitcomp
Physical Design of Mixed Signal Circuit that performs - "Post-Layout: OpenFASOC flow for 3-bit Flash ADC using TIQ comparator".
Language: Python - Size: 11.7 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
