electronic-design-automation | Topic

Topic: "electronic-design-automation"

ai4co/rl4co

A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)

Language: Python - Size: 155 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 564 - Forks: 98

OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Language: Verilog - Size: 329 MB - Last synced at: 10 months ago - Pushed at: almost 2 years ago - Stars: 538 - Forks: 146

ai4co/reevo

[NeurIPS 2024] ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolution

Language: Python - Size: 26.7 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 178 - Forks: 38

arc-research-lab/CHARM

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

Language: C++ - Size: 173 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 142 - Forks: 22

purdue-onchip/gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

Language: C++ - Size: 4.69 MB - Last synced at: 10 months ago - Pushed at: about 2 years ago - Stars: 106 - Forks: 19

byuccl/spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Language: Python - Size: 46 MB - Last synced at: 6 days ago - Pushed at: 3 months ago - Stars: 98 - Forks: 23

OpenTimer/Parser-Verilog

A Standalone Structural Verilog Parser

Language: Verilog - Size: 6.29 MB - Last synced at: 6 months ago - Pushed at: about 3 years ago - Stars: 85 - Forks: 34

ahmed-agiza/EDAViewer

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Language: JavaScript - Size: 3.09 MB - Last synced at: 5 days ago - Pushed at: over 2 years ago - Stars: 71 - Forks: 13

luckyrantanplan/nthu-route

VLSI EDA Global Router

Language: C++ - Size: 11.6 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 57 - Forks: 12

NTU-LaDS-II/FAN_ATPG

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Language: Verilog - Size: 10.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 51 - Forks: 11

PrimisAI/nexus

A powerful Python framework for orchestrating AI agents and managing complex LLM-driven tasks with ease.

Language: Python - Size: 1.1 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 50 - Forks: 3

OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Language: C++ - Size: 63.4 MB - Last synced at: 10 months ago - Pushed at: almost 3 years ago - Stars: 50 - Forks: 23

najaeda/naja-verilog

A standalone structural (gate-level) verilog parser

Language: C++ - Size: 147 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 35 - Forks: 2

srohit0/mida

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

Language: Jupyter Notebook - Size: 11.9 MB - Last synced at: about 1 month ago - Pushed at: over 6 years ago - Stars: 26 - Forks: 7

arc-research-lab/AIM

AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!

Language: C++ - Size: 427 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 22 - Forks: 4

broccolimicro/loom

design and verification of asynchronous circuits

Language: Python - Size: 9.93 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 21 - Forks: 0

cornell-zhang/HOGA

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

Language: Python - Size: 635 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 21 - Forks: 2

ycchen218/EDA-Congestion-Prediction

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.

Language: Python - Size: 60.3 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 18 - Forks: 1

LQY404/EDA-info

the awesome work, project and lab of EDA (Electronic Design Automation). continue update...

Size: 90.8 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 14 - Forks: 1

alkgrove/partlocater

Find a part on Digi-Key and import parameters into local database

Language: Python - Size: 1.55 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 14 - Forks: 3

YuanTingHsieh/ITDP

Incremental Timing-Driven Placement, problem C of ICCAD contest 2015

Language: C++ - Size: 12.1 MB - Last synced at: about 1 month ago - Pushed at: over 7 years ago - Stars: 13 - Forks: 2

EDAAC/EDAAC

EDA Analytics Central

Language: Python - Size: 232 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 12 - Forks: 8

erihsu/tf-parser

Technology file parser in Rust

Language: Rust - Size: 94.7 KB - Last synced at: 10 days ago - Pushed at: about 4 years ago - Stars: 12 - Forks: 2

shobro/ACLA

Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction

Language: Verilog - Size: 47.9 KB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 2

LukeVassallo/RL_PCB

RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).

Language: Python - Size: 15.9 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 10 - Forks: 2

madworx/robotframework-kicadlibrary

Robot Framework KiCad Library

Language: Python - Size: 222 KB - Last synced at: 28 days ago - Pushed at: over 2 years ago - Stars: 10 - Forks: 2

efabless/nix-eda

Nix derivations for EDA tools

Language: Nix - Size: 176 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 9 - Forks: 3

shages/liberty-parse

Liberty format parser

Language: Rust - Size: 34.2 KB - Last synced at: 14 days ago - Pushed at: about 1 year ago - Stars: 7 - Forks: 4

scale-lab/EDAonCloud

Characterizing and Optimizing EDA Flows for the Cloud (DATE'2021 and TCAD)

Language: Python - Size: 42.4 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 5

Circuits-and-Systems-Lab-CASlab/UPSET

UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

Language: Makefile - Size: 5.33 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 5 - Forks: 0

bics-rug/heracles

HfO2 ferroelectric capacitor compact model for circuit simulation

Language: Common Lisp - Size: 606 KB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 5 - Forks: 1

The-OpenROAD-Project/EDAAC Fork of EDAAC/EDAAC

EDA Analytics Central

Language: Python - Size: 214 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 4

byuccl/spydrnet-tmr

TMR utilities for the SpyDrNet project

Language: Python - Size: 10.7 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 2

eda-ricercatore/research-contests

A repository for research contests spanning topics from hardware security and embedded/VLSI machine learning to electronic design automation, bio design automation, and formal verification.

Language: TeX - Size: 466 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 1

ycchen218/EDA-IRdrop-Prediction

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.

Language: Python - Size: 6.31 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

fakerbaby/Flora

Flora is an new GNN-based Open Source tool can apply to Dreamplace post-processing, so that can achieve faster and more accurate layout design.

Language: Python - Size: 9.89 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 1

stevenlowery011/pymensor

Python driver for Mensor Modular Pressure Controllers

Language: Python - Size: 22.5 KB - Last synced at: 15 days ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 2

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.

Language: Python - Size: 632 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 1

Rob382/salidas-programables-mejora-de-auto-alarma-

En este proyecto yo hice el rediseño (electrónico y programas), así como modificaciones del sistema de auto alarma previamente implementado por la empresa, solucionando los problemas de consumo de energía y mejorando el circuito funcional (la parte automática) con un rediseño total.

Language: C++ - Size: 6.19 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

electronics-and-drives/MLCAD22

Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"

Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 1

cuhk-eda/split-extract

Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation

Language: C++ - Size: 1020 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 2

abhinuvpitale/ROBDD

Implementation of ROBDD in python

Language: Jupyter Notebook - Size: 1.19 MB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 1

YuanTingHsieh/ColorBalancing

Color Balancing for Double Patterning, problem E of CAD contest 2015

Language: C++ - Size: 646 KB - Last synced at: about 1 month ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 2

NooriDan/SymXplorer

A symbolic math toolbox in Python to explore the design space of analog circuits. Find possible filters for any given nodal equation set and allowed impedance connections. Size, symbolically or with SPICE, for a given AC response using Bayesian optimization or Evolutionary algorithms.

Language: Python - Size: 457 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

NYU-MLDA/ABC-RL

This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

Language: Verilog - Size: 21.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0