netlist | Topic | Ecosyste.ms: Repos

Topic: "netlist"

nturley/netlistsvg

draws an SVG schematic from a JSON netlist

Language: JavaScript - Size: 1.02 MB - Last synced at: 6 days ago - Pushed at: over 1 year ago - Stars: 686 - Forks: 89

emsec/hal

HAL – The Hardware Analyzer

Language: C++ - Size: 3.07 GB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 658 - Forks: 85

google/pcbdl 📦

PCB Design Language: A programming way to design schematics.

Language: Python - Size: 6.12 MB - Last synced at: 9 days ago - Pushed at: about 4 years ago - Stars: 176 - Forks: 23

circuitgraph/circuitgraph

Tools for working with circuits as graphs in python

Language: Verilog - Size: 10.5 MB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 115 - Forks: 14

najaeda/naja

Structural Netlist API (and more) for EDA post synthesis flow development

Language: Verilog - Size: 15.8 MB - Last synced at: 10 days ago - Pushed at: 18 days ago - Stars: 93 - Forks: 14

byuccl/spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Language: Python - Size: 46 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 88 - Forks: 21

electron-lang/electron

A mixed signal netlist language (pre-alpha)

Language: TypeScript - Size: 2.71 MB - Last synced at: 6 days ago - Pushed at: over 6 years ago - Stars: 60 - Forks: 6

najaeda/naja-verilog

A standalone structural (gate-level) verilog parser

Language: C++ - Size: 196 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 35 - Forks: 2

aaanthonyyy/CircuitNet

A hand-drawn schematic sketch recognizer and converter. Traditional object detection techniques built using OpenCV; deep learning classification powered by TensorFlow 2 using the Keras API.

Language: Jupyter Notebook - Size: 44.6 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 33 - Forks: 5

SpiceSharp/SpiceSharpParser

SPICE netlists parser for .NET

Language: C# - Size: 8.52 MB - Last synced at: 19 days ago - Pushed at: 4 months ago - Stars: 26 - Forks: 6

jimwang99/parser-for-chip-design

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

Language: Python - Size: 145 KB - Last synced at: over 1 year ago - Pushed at: almost 10 years ago - Stars: 24 - Forks: 7

arasgungore/netlist-solver

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

Language: MATLAB - Size: 531 KB - Last synced at: 16 days ago - Pushed at: over 2 years ago - Stars: 20 - Forks: 3

ganeshgore/spydrnet-physical

This is a SpyDrNet Plugin for a physical design related transformations

Language: Python - Size: 18.7 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 11 - Forks: 4

emsec/hal-benchmarks

Benchmark suite for HAL

Language: VHDL - Size: 9.16 MB - Last synced at: about 2 months ago - Pushed at: over 4 years ago - Stars: 11 - Forks: 1

akashlevy/pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

Language: SourcePawn - Size: 184 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 10 - Forks: 3

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2

jvestman/skimibowi

SKiDL Microcontroller Board Wizard

Language: Python - Size: 522 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 0

CIDARLAB/MINT

Language: ANTLR - Size: 32.2 KB - Last synced at: about 4 hours ago - Pushed at: over 7 years ago - Stars: 5 - Forks: 3

byuccl/spydrnet-tmr

TMR utilities for the SpyDrNet project

Language: Python - Size: 10.7 MB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 2

shishir-dey/vhdl-samples

Contains VHDL netlists of basic digital circuits

Language: VHDL - Size: 1.09 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0

circuitgraph/circuitsim

Perform gate-level simulations from python

Language: Python - Size: 44.9 KB - Last synced at: 15 days ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

jamestiotio/compstruct

SUTD 2020 50.002 Computation Structures Code Dump

Language: C - Size: 89.7 MB - Last synced at: 12 months ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0

chmod775/trace

Electronic PCB Programmig Language: Create an Electronic Netlist and Schematic using JavaScript and limitless automations.

Language: JavaScript - Size: 440 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

amfl/short-circuit

tile-based digital logic sandbox

Language: Python - Size: 148 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 1

SubZer0811/BE2SIM

This repository contains a python script that converts a Boolean Expression to a .SIM file (circuit netlist description).

Language: Python - Size: 4.88 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

LibrEDA/libreda-db

Layout and netlist data structures for the Rust LibrEDA framework.

Language: - Size: 903 KB - Last synced at: over 1 year ago - Stars: 3 - Forks: 2

Library for parsing netlists in the PADS Layout ASCII format (`.asc` files). It provides a structured object representation of the netlist data, making it easy to process and convert to other formats like the Yosys JSON format used for circuit analysis and visualization.

Language: TypeScript - Size: 113 KB - Last synced at: 5 days ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

pablov55/Beginner-s-Guide-to-KiCad

This guide will teach you all the basics of KiCad from schematic building to PCB design. It will also teach you how to add libraries, create your own symbols & footprints, export the drill and gerber files, and many more tips to get you started on your KiCad journey!

Language: HTML - Size: 5.29 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

muhammadtalhasami/openlane

This is my openlane repository in which we perform synthesis of our design/module.

Language: Tcl - Size: 384 KB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

rohankalbag/logic-simulator

Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: Jupyter Notebook - Size: 95.7 KB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

LCSR-lab/MODNET

MODNET (MODify NETlist): VHDL/Verilog Fault Injection system

Language: Python - Size: 112 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

LCSR-lab/NetFi3

NetFI-3: Netlist Fault Injection system - Version 3

Language: TeX - Size: 23.2 MB - Last synced at: 11 months ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

Jjateen/7T-SRAM-MCPL

This project showcases the design and simulation of a 7T MCPL SRAM using adiabatic logic for low-power efficiency, developed for ECL 312 at IIIT Nagpur. It compares the 6T and 7T SRAM designs in terms of power, energy, and stability, with simulations done in WinSpice and Microwind.

Language: SystemVerilog - Size: 3.62 MB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0