vlsi-circuits | Topic | Ecosyste.ms: Repos

Topic: "vlsi-circuits"

OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Language: Verilog - Size: 329 MB - Last synced at: 9 months ago - Pushed at: almost 2 years ago - Stars: 538 - Forks: 146

AUCOHL/DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

Language: Verilog - Size: 47 MB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 123 - Forks: 33

purdue-onchip/gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

Language: C++ - Size: 4.69 MB - Last synced at: 9 months ago - Pushed at: about 2 years ago - Stars: 106 - Forks: 19

OpenTimer/Parser-Verilog

A Standalone Structural Verilog Parser

Language: Verilog - Size: 6.29 MB - Last synced at: 5 months ago - Pushed at: about 3 years ago - Stars: 85 - Forks: 34

luckyrantanplan/nthu-route

VLSI EDA Global Router

Language: C++ - Size: 11.6 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 57 - Forks: 12

ehw-fit/evoapproxlib

Library of approximate arithmetic circuits

Language: Verilog - Size: 57.8 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 54 - Forks: 17

OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Language: C++ - Size: 63.4 MB - Last synced at: 9 months ago - Pushed at: over 2 years ago - Stars: 50 - Forks: 23

imsanjoykb/Electrical-And-Electronic-Engineering-Course-Materials

Electrical And Electronic Engineering Course Materials

Language: MATLAB - Size: 1.68 GB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 35 - Forks: 3

srohit0/mida

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

Language: Jupyter Notebook - Size: 11.9 MB - Last synced at: 20 days ago - Pushed at: over 6 years ago - Stars: 26 - Forks: 7

SubZer0811/VLSI

All the projects and assignments done as part of VLSI course.

Language: Verilog - Size: 6.45 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 15 - Forks: 4

paripath/cdf

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

Language: C++ - Size: 510 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 12 - Forks: 4

levibyte/pyqt_genetic_algo

genetic algorithm usage for routing optimization ( pyqt )

Language: Python - Size: 46.9 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 11 - Forks: 3

ali-ece/Design-of-optimal-CMOS-ring-oscillator-using-an-intelligent-optimization-tool

This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect tradeoff between the contradictory objective functions in CMOS RO optimal design. This tool is applied for intelligent estimation of the circuit parameters (channel width of transistors), which have a decisive influence on RO specifications. Along the optimal RO design in an specified range of oscillaton frequency, the Power Consumption, Phase Noise, Figure of Merit (FoM), Integration Index, Design Cycle Time are considered as objective functions. Also, in generation of Pareto front some important issues, i.e. Overall Nondominated Vector Generation (ONVG), and Spacing (S) are considered for more effectiveness of the obtained feasible solutions in application. Four optimization algorithms called Multi-Objective Genetic Algorithm (MOGA), Multi-Objective Inclined Planes system Optimization (MOIPO), Multi-Objective Particle Swarm Optimization (MOPSO) and Multi-Objective Modified Inclined Planes System Optimization (MOMIPO) are utilized for 0.18-mm CMOS technology with supply voltage of 1-V. Baesd on our extensive simulations and experimental results MOMIPO outperforms the best performance among other multi-objective algorithms in presented RO designing tool.

Size: 10.9 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 9 - Forks: 2

tharunchitipolu/Multi-operations-toolbox-with-baugh-wooley-multiplier

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

Language: Verilog - Size: 52.7 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 7 - Forks: 1

trojanink/vlsi-cmos-inverter-design-magic

VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic

Size: 957 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 1

SalomeDevkule7/Carry-Select-Adder-8-bit

VLSI Physical Design

Size: 271 KB - Last synced at: 5 months ago - Pushed at: almost 7 years ago - Stars: 5 - Forks: 1

RarityBrown/blog

Some ramblings about my major. 一些有关我的专业的碎碎念

Size: 797 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 2 - Forks: 0

MuballighHossain/Very-Large-Scale-Integration-BRAC-University

Size: 19.2 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

MuballighHossain/VLSI_FSM_Verilog_Simulation

Language: Verilog - Size: 2.96 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 1

sujoyyyy/VLSI

Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.

Language: Verilog - Size: 6.68 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

Saadia-Hassan/Simulation-of-Memristor-Based-Full-Adder

LTSpice simulation software is used to study the behavior of a Memristor. Different logic gates like NOR, NAND and XOR were modelled and simulated followed by the simulation of a memristor based full-adder.

Language: AGS Script - Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

ShogunYash/My-Code-Space

This contains my course assignments of SEM 3

Language: Python - Size: 4.86 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 1

LijinWilson/CMOS-NAND-gate-2-input-NAND-gate

This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.

Size: 0 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0