Topic: "verilog-a"
pascalkuthe/OpenVAF
An innovative Verilog-A compiler
Language: Rust - Size: 10.5 MB - Last synced at: 30 days ago - Pushed at: 10 months ago - Stars: 149 - Forks: 31
dwarning/VA-Models
Verilog-A simulation models
Language: Pascal - Size: 13.6 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 61 - Forks: 10
ACMmodel/MOSFET_model
A simple MOSFET model with only 5-DC-parameters for circuit simulation
Size: 7.76 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 29 - Forks: 5
akashlevy/pyxbar
Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations
Language: SourcePawn - Size: 184 MB - Last synced at: 2 days ago - Pushed at: over 5 years ago - Stars: 13 - Forks: 4
akashlevy/WP-RRAM-SPICE-Model
A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley
Size: 1.95 KB - Last synced at: 2 days ago - Pushed at: over 4 years ago - Stars: 10 - Forks: 3
thennen/Synaptogen
A fast generative model for stochastic memory cells
Language: Julia - Size: 395 KB - Last synced at: 26 days ago - Pushed at: 8 months ago - Stars: 6 - Forks: 0
gnucap/gnucap-adms
defunct. use repo on savannah
Size: 1.39 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 2
RarityBrown/blog
Some ramblings about my major. 一些有关我的专业的碎碎念
Size: 851 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 3 - Forks: 0
NVerilog/NVerilogParser
A Verilog-AMS parser for .NET
Language: C# - Size: 668 KB - Last synced at: 7 months ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 4
pouryahoseini/Genetic-Algorithm-Processor
A digital genetic algorithm processor
Language: Verilog - Size: 3.99 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 1
keikawa/Verilog-A-photonic-model-library
Verilog-A model library for photonic devices and components used in electro-optic co-simulation
Size: 323 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 1
rpm2003rpm/vagen
Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
Language: Python - Size: 1.6 MB - Last synced at: 3 days ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
pyadms/pyadms
Python Automatic Device Model Synthesizer
Language: C++ - Size: 10.4 MB - Last synced at: 28 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
ShabbyGayBar/VerilogAmsLib
Library of Verilog-AMS models
Size: 5.86 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
rpm2003rpm/stg2veriloga
converts a stg (.g file generated by workcraft) to a verilogA model
Language: Python - Size: 141 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
posvirus/RTE-Sim
Compact model for light propagation simulation in fNIRS systems
Size: 760 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
nikacvet/vscode-verilogA
Language support in Visual Studio Code for VerilogA
Language: TypeScript - Size: 1020 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
