mips-processor | Topic | Ecosyste.ms: Repos

Topic: "mips-processor"

mhyousefi/MIPS-pipeline-processor

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

Language: Verilog - Size: 1.54 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 95 - Forks: 27

aeris170/MARS-Theme-Engine

It's all coming back into focus!

Language: Java - Size: 14.5 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 65 - Forks: 9

neelkshah/MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Language: Verilog - Size: 138 KB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 64 - Forks: 13

Ingenic-community/linux

Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.

Language: C - Size: 246 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 27 - Forks: 6

alirezakay/RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Language: VHDL - Size: 2.52 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 27 - Forks: 5

edoardottt/asm-snippets

Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree :floppy_disk:

Language: Assembly - Size: 710 KB - Last synced at: 2 months ago - Pushed at: 7 months ago - Stars: 19 - Forks: 5

prantoamt/16bit_processor_design

Size: 292 KB - Last synced at: about 1 month ago - Pushed at: over 6 years ago - Stars: 12 - Forks: 6

jasonlovescoding/MIPS32CPU-5stage-pipelined

A 5-stage pipelined mips32 processor

Language: Verilog - Size: 2.5 MB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 8 - Forks: 1

yasnakateb/MIPSProcessor

🔮 A 32-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 230 KB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 7 - Forks: 0

JosiahMendes/MIPS32-T501

A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

Language: Verilog - Size: 1.04 MB - Last synced at: 6 months ago - Pushed at: almost 4 years ago - Stars: 7 - Forks: 2

alabarjasteh/fum-mips

MIPS simulator written in Go

Language: Go - Size: 583 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 6 - Forks: 2

LIU42/Processor

《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。

Language: Verilog - Size: 97.7 KB - Last synced at: 4 days ago - Pushed at: 6 months ago - Stars: 5 - Forks: 0

holden-davis-uca/MARS-UCA

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

Language: HTML - Size: 55.6 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1

yasnakateb/PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 75.2 KB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 0

mongrelgem/cMIPS

A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

Language: Verilog - Size: 4.09 MB - Last synced at: 4 months ago - Pushed at: almost 6 years ago - Stars: 5 - Forks: 0

Gripnook/mips-pipelined-processor

A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.

Language: VHDL - Size: 14.8 MB - Last synced at: 3 months ago - Pushed at: about 8 years ago - Stars: 5 - Forks: 0

daltonbr/MIPS

simulator of a MIPS processor in C

Language: C - Size: 1.16 MB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 5

flozzone/DDCA

Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.

Language: VHDL - Size: 1.61 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 3

aeris170/Dark-Side-of-MARS

DEPRECATED!!! An (almost) fully functional theme engine for MARS.

Language: Java - Size: 3.65 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 0

cwalk/Mini-Processor-Simulator

Core part of a mini processor simulator called MySPIM using the C language on a Unix/Linux platform. MySPIM demonstrates some functions of the MIPS processor as well as the principle of separating the data-path from the control signals of the MIPS processor. The MySPIM simulator reads in a file containing MIPS machine code (in a specified the format) and simulates what MIPS does cycle-by-cycle (single-cycle data path).

Language: C - Size: 174 KB - Last synced at: over 2 years ago - Pushed at: about 9 years ago - Stars: 4 - Forks: 4

psh4607/32-bit-MIPS-Processor-Pipeline

A 32-bit MIPS processor developed in Verilog based on pipeline

Language: C - Size: 5.87 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

z64me/minimips64

the tiniest MIPS R4300i assembler and disassembler

Language: C - Size: 115 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

hakula139/MIPS-CPU 📦

A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog

Language: SystemVerilog - Size: 3.01 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

nimaiji/MIPS-Pipeline-CPU

💻 MIPS Pipeline Processor simulator

Language: Python - Size: 313 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 0

arlotfi79/MIPS-Processor 📦

A 32-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 24.4 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

fardinanam/CSE-306-Computer-Architecture-Sessional

Assignments done in CSE306 course offered by CSE, BUET

Language: C++ - Size: 821 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 1

kalhorghazal/Mips-MultiCycle

Mips Multi-Cycle, Computer Architecture course, University of Tehran

Language: SystemVerilog - Size: 18.6 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0

mcai/heo

Heo is a cycle-accurate multicore architectural simulator written in Go.

Language: C - Size: 108 MB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 1

NSU-ACM-SC/16bit_processor_design

Size: 292 KB - Last synced at: about 1 month ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

AbdallahReda/MIPSProcessor

Verilog Description for a 32bit MIPS Processor

Language: Verilog - Size: 8.83 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 1

mostafaelhoushi/MIPS-Q

VHDL model, assembler, and C/C++ compiler for MIPS-Q: a MIPS processor with a quantum processing module.

Language: VHDL - Size: 2.01 MB - Last synced at: 2 months ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

JonayedMohiuddin/8bit-PIPELINED-MIPS

An 8-bit MIPS processor designed in Logisim, featuring pipelined and non-pipelined architectures, a custom assembler for MIPS assembly to binary conversion, extended I/O peripheral support, and some playable Game implemented in MIPS assembly.

Language: C++ - Size: 37.3 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

guntas-13/mips-processor-basys3

Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor

Language: Verilog - Size: 92.7 MB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 1

avnlk/MIPS_Processor

Processor designed to execute machine code instructions generated using an MIPS assembler. The assembler takes the machine code as input and performs the required operations.

Language: Python - Size: 111 KB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

AnshikSahu/Pipeline_Simulator-COL216-

Simulator for MIPS pipeline

Language: C++ - Size: 10.5 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

IgnacioChirinos/MIPS-VHDL-Vivado

MIPS processor that performs matrix multiplication 3x3 based on VHDL and implemented in XILINX

Language: VHDL - Size: 296 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

cgsdfc/mips-pipeline-cpu.verilog

A simple five-stage pipeline MIPS CPU in Verilog.

Language: Assembly - Size: 45.1 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

anupbhowmik/Computer-Architecture-CSE-306

This is a repository containing all the simulations and reports of CSE-306 Computer Architecture Sessional.

Language: C++ - Size: 550 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

rvmosquera/CS2201

Computer Architecture

Language: Jupyter Notebook - Size: 358 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

sotheanithsok/CECS-225-Collection 📦

Designing and building multiple digital circuits.

Language: C - Size: 3.81 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

akankshac-073/MIPS-5-stage-pipelined-control-and-datapath

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.

Language: Verilog - Size: 20.5 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 1

ShivanshRakesh/mips-processor

A 2-stage Pipelined MIPS Processor in Verilog

Language: Verilog - Size: 141 KB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

aminhm/MIPS-CPU-simulator

Language: Python - Size: 3.45 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

IanArko/MIPS_CPU

This is a functioning MIPS CPU designed in Verilog to run an an xilinx fpga.

Language: Verilog - Size: 3.76 MB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

kalhorghazal/Mips-SingleCycle

Mips Single-Cycle, Computer Architecture course, University of Tehran

Language: SystemVerilog - Size: 21.5 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

llaet/MIPS-ToBinaryConverter

Computers Architecture university project. MIPS document converter to binary computer language.

Language: Java - Size: 87.9 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

YanzheL/mips_soft_cpu

Course project for Computer Design and Practice at HIT.

Language: VHDL - Size: 17.8 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

JB-toriel/MIPS_Emulator

MIPS processor emulator in C [school project]

Language: C - Size: 636 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

HugeCH38/MIPS

🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。

Language: VHDL - Size: 179 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 1

mateuspinto/FPGA_SystemVerilog_MIPS_Pipeline-TP1-OC2-UFV

A complete hardware description of a pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA. It also has the ALMa Mips Mounter built-in.

Language: SystemVerilog - Size: 2.78 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

matthewdargan/MIPS-Processor 📦

An implementation of a MIPS processor that supports a majority of the MIPS instruction set

Language: Python - Size: 10.9 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

Jesusiteso/Anguiano_Valadez_Practica_2

Practica 2 de Arquitectura computacional

Language: Verilog - Size: 80.1 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

Subangkar/Computer-Architecture-CSE-306-BUET

Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET

Language: VHDL - Size: 200 MB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 1

HuangDave/MIPS

Single-Cycle and 5-stage Pipelined SoC

Language: Verilog - Size: 44.3 MB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

JungleEngine/Project_ARCH_2

Simplified implementation of MIPS pipelined processor

Language: VHDL - Size: 272 KB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

balos1/MIPS_Single_Cycle

This is project is a MIPS Single-Cycle processor with a cache for data memory.

Language: SystemVerilog - Size: 945 KB - Last synced at: 2 months ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 0

Vihaan004/mips-multicycle-processor

A modular MIPS multicycle processor implementation focused on simulation, analysis, and educational exploration of processor design.

Language: Tcl - Size: 1.71 MB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 0 - Forks: 0

cybersecurity-dev/MIPS-Embedded-Toolkit

MIPS based Embedded Device Toolkit

Size: 7.81 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

ayeshathoi/CSE-306

Computer Architecture Hardware Sessional

Size: 9.96 MB - Last synced at: 4 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

sushi0706/mips-pipeline-processor

5-stage pipelined 32-bit MIPS processor

Language: Verilog - Size: 1.01 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

ahmd-kamel/Single-Cycle_MIPS

Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.

Language: Verilog - Size: 982 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

TalesNogueira/Compiler-C-Minus

C- compiler made for a unicycle processor based on MIPS with RISC instruction set. / Compilador de C- feito para um processador unicíclico baseado em MIPS com conjunto de instrução RISC. / FLEX | YACC-Bison

Language: Lex - Size: 5.86 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

JavidChaji/FUM-Computer-Architecture-Single-Cycle-MIPS-Processor

Single Cycle MIPS Processor implementation, Computer Assignment for Computer Architecture course in Ferdowsi University of Mashhad

Language: Verilog - Size: 728 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

gautamop01/CS211-Computer-Architecture

Learned as a part of Computer architecture Course

Language: Assembly - Size: 36.5 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

mutayyab01/Mips-Projects

MIPS Architecture Project (MARS)

Language: Assembly - Size: 4.88 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

mhshabani79/MIPS-pipeline

MIPS Verilog implementation with pipeline , Cache and SRAM

Language: Verilog - Size: 1.21 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 1

mhshabani79/MIPS-multi-cycle

MIPS multi cycle Verilog Implementation

Language: SystemVerilog - Size: 1.56 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

mhshabani79/MIPS-single-cycle

MIPS Single cycle Verilog Implementation

Language: SystemVerilog - Size: 1.06 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

DieaAbdeltwab/Pipelined-MIPS-Processor

Single Cycle and Pipelined MIPS Processor

Size: 1.72 MB - Last synced at: 11 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

malakadel/PIPELINED-PROCESSOR-IMPLEMENTATION

Is implementation for simple pipeline processor (MIPS processor ) , with logisim software .

Size: 38.1 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

MaxEnerGyzz/MIPS-project

An MIPS processor emulator, our C programming end of the course project. (school promotion 2024)

Language: C - Size: 1.72 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

ECE473-2021/mips_cpu

MIPS-Like CPU written (mostly) in verilog

Language: Verilog - Size: 669 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

aamanrebello/MIPS1-processor-simulator

Accepts input binary file and provides return code for $v0 (register $2). Simulates behaviour of processor with respect to registers, PC etc.

Language: C++ - Size: 167 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

kalhorghazal/Computer-Architecture-Course-Projects

👷‍♀️Computer Architecture Course Projects, University of Tehran

Size: 1.95 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

Abhishek-Sharma94/Single-cycle-MIPS-processor

This project is about simulating the single cycle MIPS processor using Matlab and Xilinx tools. Separate files are created for each component in the MIPS processor.

Language: MATLAB - Size: 54.7 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

GabrielGiurgica/8-bit-MIPS-Processor

A Verilog implementation of an 8-bit MIPS processor

Language: Verilog - Size: 589 KB - Last synced at: 10 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

furkanozev/MIPS-Processor

A 32 bit Mips processor that can run some J type R type and I type instructions written in structural VerilogHDL.

Size: 1.75 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

paulohepimentel/mips

Implementation of a simplified version of the MIPS data path

Language: Verilog - Size: 294 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0

blroot/MIPS-Segmentado

Procesador MIPS segmentado

Language: VHDL - Size: 140 KB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

mohsenfayyaz/MIPS_pipeline

Language: Verilog - Size: 205 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

david-palma/mips-32bit-encoder

C implementation of a 32-bit assembly instruction encoder for MIPS processors, designed to convert MIPS assembly instructions into their corresponding machine code formats for execution on MIPS-based systems.

Language: C - Size: 5.86 KB - Last synced at: 2 months ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

shaye059/Mips-Processor

A MIPS processor written in VHDL and run on an Intel Cyclone IV

Language: VHDL - Size: 61.5 KB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

szymonkobus/MIPS_simulator

Language: C++ - Size: 12.9 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

abhilash-neog/Verilog-Programming

Verilog Lab work at BITS Pilani

Language: Verilog - Size: 3.2 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

Shadolio/ca-mips 📦

Simulating a 32-bits single-piepline MIPS processor.

Language: Verilog - Size: 1.61 MB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0