cyber-anubis/The-HACK-General-Purpose-Computer

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.

Language: Python - Size: 151 KB - Last synced at: 2 months ago - Pushed at: over 4 years ago - Stars: 99 - Forks: 5

hoangsonww/Digital-Design-Labs

🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.

Language: Assembly - Size: 712 KB - Last synced at: 11 days ago - Pushed at: 12 days ago - Stars: 23 - Forks: 12

arasgungore/NandGame

Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

Size: 4.85 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 14 - Forks: 1

komed3/8-bit-alu

Project to build an 8-bit arithmetic logic unit (ALU) consisting only of transistors.

Size: 13.1 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 6 - Forks: 2

Anonto050/CSE-306-Computer_Architecture

Contains codes and designs of computer architecture assignments

Language: Makefile - Size: 11.6 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0

BRAINIAC2677/CSE-306-Computer-Architecture

Contains the project resources of the course CSE306. These were group projects.

Language: TeX - Size: 12 MB - Last synced at: about 1 month ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

zhuzhu81998/Arithmetic-Logic-Unit

An ALU designed for the coursework "Digital Design and Computer Architecture" given by Prof. Onur Mutlu at ETH Zurich (Spring 2023)

Language: Verilog - Size: 5.86 KB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

fardinanam/CSE-306-Computer-Architecture-Sessional

Assignments done in CSE306 course offered by CSE, BUET

Language: C++ - Size: 821 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 1

COSys-Research/Fixed-Posit

Repository accompanying the paper "Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications" published in IEEE Transactions on Circuits and Systems II

Language: Python - Size: 107 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 2

cerus/arithmetic-logic-unit

ALU representation in Rust

Language: Rust - Size: 12.7 KB - Last synced at: about 1 month ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0

JinBean/16bitALU

Building a 16 bit Arithmetic Logic Unit using the Mojo v3 FPGA and Lucid

Language: Verilog - Size: 42 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1

sithulaka/8-bit-ALU-Implementation

This repository demonstrates an 8-bit Arithmetic Logic Unit (ALU) built using IoT components like a Raspberry Pi Pico, seven-segment displays, and SN74LS83N Adder ICs to perform binary addition.

Language: Python - Size: 1020 KB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

BUR4KBEY/digital-design-4-bit-alu

This project implements a 4-bit ALU with six operations using Verilog on the Tang Nano 9K FPGA. It includes a detailed circuit simulation, real-life construction, and comprehensive documentation for open-source use.

Language: Verilog - Size: 58.6 KB - Last synced at: 22 days ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

mrtaz77/Computer-Architecture

Computer Architecture Projects

Language: TeX - Size: 14.4 MB - Last synced at: 18 days ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

ryanlemes/ALU

ALU created in VHDL

Language: VHDL - Size: 4.88 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 1

jamestiotio/ehp

SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project

Language: Python - Size: 31.5 MB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

anupbhowmik/Computer-Architecture-CSE-306

This is a repository containing all the simulations and reports of CSE-306 Computer Architecture Sessional.

Language: C++ - Size: 550 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

patel-soham/16-bit-microprocessor-verilog

A final year undergraduate major project. (Dec 2019 - Mar 2020)

Language: C - Size: 3.06 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

dmittrj/ALU-jet

Software simulation of computer operation

Language: C# - Size: 126 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

tristan-oa/ALU-in-VHDL

Building an ALU using VHDL

Size: 5.21 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

paramrathour/Team-Rocket

Language: VHDL - Size: 11.4 MB - Last synced at: 29 days ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

JacemHaggui/Building-a-Computer-from-Scratch

My work on the project-based course NAND2TETRIS.

Language: Assembly - Size: 4.96 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

barannmeisterr/32-Bit-ALU-Design

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

Language: SystemVerilog - Size: 0 Bytes - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

ayeshathoi/CSE-306

Computer Architecture Hardware Sessional

Size: 9.96 MB - Last synced at: about 2 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

shahriar-raj/CSE_306-Computer-Architecture-Sessional

This repository contains all home and lab assignments for the CSE 306 : Computer Architecture Sessional course, part of our Term-1, Level-3 curriculum. It applies theories from CSE 305 to implement different components of computer architecture..

Size: 3.13 MB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

zyx7k/ngspice-4-Bit-ALU

Implementing a 4-Bit ALU in Ngspice

Language: SourcePawn - Size: 3.26 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

zyx7k/Verilog-4-Bit-ALU

Implementing a 4-Bit ALU in Verilog

Language: Verilog - Size: 57.6 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

rakshitharnayak/RISC--V-Processor

RISC V PROCESSOR DESIGN IN VERILOG

Language: Verilog - Size: 27.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

HR-Fahim/Full-Single-Cycle-Pipelined-Datapath-With-Control-Unit-Using-16bit-ALU

In a Single Cycle Datapath, each of the Datapath's components carries out an instruction in one cycle. Therefore, no Datapath component may be utilized more than once each cycle.

Size: 459 KB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

mymermer/Computer_Organization_Project_1

Computer Organization 1st Project

Language: Verilog - Size: 3.24 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 1

emircetinmemis/memory-management-simulation

The project is a Python-based simulation of a computer processor that enables users to explore the various components and functions of a processor in a controlled environment.

Language: Python - Size: 291 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

vijaysatchi/minecraft

Making computer architecture parts from a CPU on minecraft.

Size: 1.22 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

serpest/ALU

Simple arithmetic logic unit (ALU) implementation in SystemVerilog

Language: SystemVerilog - Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

EnesErcin/Pipelined_Multipication_Module

An attempt of creating faster multiplication circuit with HDL VHDL

Language: VHDL - Size: 146 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Ibraam-Nashaat/Arithmetic-Logic-Unit

ALU capable of adding, subtracting, multiplying and calculating the remainder of two signed 3-bits numbers.

Size: 167 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

abdallahalkashawy/Assembly-Implementation

implement a subset of the basic computer to do a simulation for a memory system and an arithmetic unit and a group of registers.

Size: 12.7 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

archy-co/l4logic

Logic elements constructor

Language: Python - Size: 6.4 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1

Gabrielgr01/Proyecto2_ALU

Diseño e implementación de una Unidad Aritmético Lógica (ALU).

Language: TeX - Size: 6.1 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

InvincibleJuggernaut/ALU

Design for 4 bit ALU with essential logical and arithmetic modules.

Language: Verilog - Size: 1.11 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

YingjieQiao/Comp-Struct-2D

16-bit ripple carry adder. ISTD 2D challenge, 50.002 section.

Language: Python - Size: 374 KB - Last synced at: about 2 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

yasser-aboelgheit/ALU-VHDL

implementing ALU using VHDL and ModelSim as IDE

Size: 138 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0