datapath | Topic | Ecosyste.ms: Repos

Topic: "datapath"

Belphemur/node-json-db

A simple "database" that use JSON file for Node.JS.

Language: TypeScript - Size: 5.04 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 814 - Forks: 66

loxilb-io/loxilb-ebpf

loxilb ebpf sub-module

Language: C - Size: 4.32 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 30 - Forks: 13

snowzjx/liteflow

A Hybrid Framework to Build High-performance Adaptive Neural Networks for Kernel Datapath

Language: C - Size: 476 KB - Last synced at: 6 months ago - Pushed at: about 2 years ago - Stars: 25 - Forks: 6

brunocampos01/organizacao-e-arquitetura-de-computadores

Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).

Language: Assembly - Size: 54.3 MB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 18 - Forks: 1

techcentaur/CPU-ARM

Design and implementation of a complete ARM based CPU.

Language: VHDL - Size: 973 KB - Last synced at: 6 months ago - Pushed at: about 7 years ago - Stars: 15 - Forks: 3

brilacasck/micro-acc-systemc

simulating connection of micro processor and accelerator on a bus context with systemc language

Language: C++ - Size: 625 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 8 - Forks: 1

respinha/mips-systemc

Assignment from the Advanced Computer Architecture class.

Language: C++ - Size: 15.6 MB - Last synced at: about 1 year ago - Pushed at: over 8 years ago - Stars: 7 - Forks: 1

zarif98sjs/CSE-306-Computer-Architecture

CSE-306-Computer-Architecture Offline / Assignment on ALU, Floating Point Adder and 8 bit MIPS Datapath along with pipelining

Language: C++ - Size: 19.1 MB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 6 - Forks: 3

hannahvsawiuk/Simple-RISC-Machine

Finite state machine controlled RISC machine

Size: 13.7 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 4 - Forks: 0

taffarel55/electronic-calculator

Calculadora eletrônica feita no simulador Circuit Verse, realiza soma de 2 números de 0 a 99, conversão bin2dec e dec2bin.

Language: Shell - Size: 12.3 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

burzt/cpu-datapath-webapp

Interactive CPU Datapath Simulator made to educate students on the MIPS architecture

Language: JavaScript - Size: 1.36 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

alibrahimzada/Computer-Organization-Assignments-Spring21

Computer Organization Projects from Spring 2021 in Marmara University, Istanbul, Turkey

Language: Assembly - Size: 2.5 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0

NegarMirgati/Matrix-Multiplication

Language: Verilog - Size: 3.53 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

aben20807/computer_organization

1052_計算機組織 COMPUTER ORGANIZATION

Language: Verilog - Size: 2.48 MB - Last synced at: 3 months ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 0

andreabazerla/ops-wheel

Car system to signal a wheel punctured on display developed in SIS

Size: 1010 KB - Last synced at: about 2 years ago - Pushed at: over 9 years ago - Stars: 2 - Forks: 0

pabloDeputter/16-bit-custom-CPU-logisim

Design and implementation of a 16-bit CPU in Logisim, featuring a custom datapath, ALU, memory operations, branching, and exception handling. Created for the "Computer Systems & Architecture" 1st bachelor course at the University of Antwerp.

Language: Python - Size: 5.58 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

mattiadane/Rock-Paper-Scissors-Circuit

University project about the game rock-paper-scissors

Language: SystemVerilog - Size: 15.6 KB - Last synced at: 14 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

jamestiotio/ehp

SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project

Language: Python - Size: 31.5 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

saliherdemk/Mips-Datapath-Simulator

This is a website for demonstration of how most of the basic instructions work in MIPS architecture

Language: JavaScript - Size: 2.38 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Amir-Shamsi/Multicycle-MIPS-in-Verilog

MIPS Multicycle CPU design in Verilog

Language: Verilog - Size: 2.93 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

eneskzlcn/Datapath

A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.

Size: 73.2 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

Agha-Muqarib/RV32-Single-Cycle-Datapath-Logism

This repository contains Risc V 32 bit single cycle data path simulated on Logism upon loading instructions.

Size: 170 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

lucianobajr/risc-v

datapath risc-v with pipeline

Language: Verilog - Size: 51.8 KB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

CedricLeclercq/UA-CS-BSc1_Logisim-Datapath

A full datapath made in Logisim. Made in the first bachelor of computer science at the University of Antwerp.

Size: 569 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 1

kalhorghazal/House-Price-Prediction-in-Verilog

📈 House Price Prediction in Verilog, Computer Architecture course, University of Tehran

Language: Verilog - Size: 21.5 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

vipul43/RISC_V_architecture_design

designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE

Language: Verilog - Size: 2.15 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

HanxinHua/Processor-Core-Design

Language: VHDL - Size: 10.3 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

michaelmortensen-m4y/Michael_RISC-V_Chisel

RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA

Language: Scala - Size: 3.03 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

jasonhsu93/CPU-Classic-RISC-Pipeline-Machine

Made a fully functional CPU model capable of performing essential computing tasks, such as executing instructions from memory, handling data with load and store operations.

Language: SystemVerilog - Size: 48.8 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

rnibhriain/computer-architecture-1

Processor VHDL :floppy_disk: assignments for module: CSU22022

Language: VHDL - Size: 2.6 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

shahed22/Architectural-Design-for-Bus-interface-connected-with-LFSR

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

Language: Verilog - Size: 208 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

MarcoBendinelli/VHDL-Histogram-Equalization-Module

VHDL module for histogram equalization, aiming to enhance image contrast using digital circuit design techniques in VHDL

Language: VHDL - Size: 4.25 MB - Last synced at: 16 days ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Aledpl5/Rock-Paper-Scissors-Circuit

Uni project about the game rock-paper-scissors

Language: SystemVerilog - Size: 13.7 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

otabek7/Datapath_Components_2

Language: Verilog - Size: 218 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

HR-Fahim/Full-Single-Cycle-Pipelined-Datapath-With-Control-Unit-Using-16bit-ALU

In a Single Cycle Datapath, each of the Datapath's components carries out an instruction in one cycle. Therefore, no Datapath component may be utilized more than once each cycle.

Size: 459 KB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

gautamop01/CS211-Computer-Architecture

Learned as a part of Computer architecture Course

Language: Assembly - Size: 36.5 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

lauracolazzo/logic-circuit-design-2022

Design of hardware component in VHDL for Logic Circuit Design course at PoliMi

Language: VHDL - Size: 2.31 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

0marAmr/Single_Cycle_RISC-V_processor

Language: Verilog - Size: 563 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

ILoveBacteria/CA-project-mips Fork of ngnma/CA-project-mips

My Computer Architecture project

Language: SystemVerilog - Size: 22.5 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

jurasans/RGBEasyUnityIntegration

capture card texture for unity using RBGEASY for DATAPATH capture cards

Language: C# - Size: 35.2 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

dudufalvo/fpga-projects

some mini-projects, developed in my digital system's class, based on: combinational/sequential logic design, hardware description languages (VHDL), datapath components, register-transfer level (RTL) design and introduction to programmable processors, with a physical implementation in SSI IC's, ASIC's, FPGA's, PLD's.

Size: 54.3 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0