instruction-set-architecture | Topic

Topic: "instruction-set-architecture"

hlorenzi/customasm

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

Language: Rust - Size: 5.26 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 958 - Forks: 66

Maratyszcza/Opcodes

Database of CPU Opcodes

Language: Python - Size: 6.55 MB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 252 - Forks: 44

gabrieldim/Assembly-MIPS-Instruction-Set

Assembly program with the MIPS instruction set

Language: Assembly - Size: 3.91 KB - Last synced at: about 2 months ago - Pushed at: over 4 years ago - Stars: 99 - Forks: 1

mikeroyal/AMX-Guide

Advanced Matrix Extensions (AMX) Guide

Language: C++ - Size: 44.9 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 92 - Forks: 7

edanor/umesimd

UME::SIMD A library for explicit simd vectorization.

Language: C++ - Size: 5.89 MB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 91 - Forks: 16

scarv/xcrypto

XCrypto: a cryptographic ISE for RISC-V

Language: Verilog - Size: 2.03 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 81 - Forks: 10

AluVM/aluvm

AluVM: RISC functional machine base implementation

Language: Rust - Size: 1.42 MB - Last synced at: about 20 hours ago - Pushed at: about 22 hours ago - Stars: 62 - Forks: 23

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Language: Verilog - Size: 1.51 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 62 - Forks: 26

kcelebi/riscv-assembler

RISC-V Assembly code assembler package for Python.

Language: Python - Size: 1.77 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 41 - Forks: 12

TomerAberbach/mano-simulator

🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.

Language: Java - Size: 1.26 MB - Last synced at: 9 days ago - Pushed at: 10 months ago - Stars: 38 - Forks: 15

sjohann81/hf-risc

HF-RISC SoC

Language: C - Size: 5.2 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 33 - Forks: 37

aofarmakis/Nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

Language: Verilog - Size: 4.01 MB - Last synced at: 4 months ago - Pushed at: 8 months ago - Stars: 32 - Forks: 0

alirezakay/RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Language: VHDL - Size: 2.52 MB - Last synced at: 4 months ago - Pushed at: about 4 years ago - Stars: 27 - Forks: 5

dmjio/LC3

:floppy_disk: The LC3 virtual machine

Language: Haskell - Size: 22.5 KB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 23 - Forks: 2

sdasgup3/parallel-processor-design

Super scalar Processor design

Language: Verilog - Size: 137 KB - Last synced at: 4 months ago - Pushed at: almost 11 years ago - Stars: 21 - Forks: 3

katamaran-project/katamaran

Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.

Language: Rocq Prover - Size: 6.65 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 18 - Forks: 4

celebi-pkg/riscv-assembler

RISC-V Assembly code assembler package for Python.

Language: Assembly - Size: 344 KB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 18 - Forks: 10

scarv/scarv-cpu

SCARV: a side-channel hardened RISC-V platform

Language: Verilog - Size: 1.37 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 18 - Forks: 6

yonseicasl/Kite

Kite: Architecture Simulator for RISC-V Instruction Set

Language: C++ - Size: 2.82 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 14 - Forks: 5

ryukzak/wrench

Wrench - is a tool for educating computer architecture.

Language: Haskell - Size: 603 KB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 13 - Forks: 21

Mograsim-Team/Mograsim

Modular Graphical Simulator for Teaching Microprogramming

Language: Java - Size: 4.5 MB - Last synced at: 8 days ago - Pushed at: 7 months ago - Stars: 12 - Forks: 1

orbit-systems/aphelion

64-bit RISC CPU Architecture

Size: 4.31 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 0

mannasoumya/vm-go

Stack Based Virtual Machine in Golang

Language: Go - Size: 4.88 MB - Last synced at: 14 days ago - Pushed at: 5 months ago - Stars: 10 - Forks: 3

david-palma/mips-32bit

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

Language: VHDL - Size: 366 KB - Last synced at: about 2 months ago - Pushed at: about 6 years ago - Stars: 8 - Forks: 1

player400/pi

My very own CPU architecture! Emulator availible!

Language: C++ - Size: 435 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 6 - Forks: 0

angrysky56/MetaTransformers-Fractal-Workflow-System

This repository contains the codebase for the MetaTransformers Fractal Workflow System, a comprehensive framework for managing and orchestrating complex workflows. The system is designed to handle a wide range of data types and workflows, from simple data processing to complex AI-driven transformations.

Language: Python - Size: 239 MB - Last synced at: 3 months ago - Pushed at: 6 months ago - Stars: 6 - Forks: 1

wisk/isabelle

Instruction Set Architecture Description Format

Language: Python - Size: 211 KB - Last synced at: over 2 years ago - Pushed at: almost 9 years ago - Stars: 6 - Forks: 3

Didula98/Building-a-Simple-Processor

Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL

Language: Verilog - Size: 7.97 MB - Last synced at: 29 days ago - Pushed at: about 3 years ago - Stars: 5 - Forks: 0

levindoneto/MIPS

Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.

Size: 1.17 MB - Last synced at: over 2 years ago - Pushed at: almost 9 years ago - Stars: 5 - Forks: 0

marceldobehere/goofy-cpu

a goofy 8 bit cpu

Language: C# - Size: 3.85 MB - Last synced at: 16 days ago - Pushed at: about 1 year ago - Stars: 4 - Forks: 0

hohaicongthuan/RV64IF 📦

RISC-V 64-bit with 32-bit floating point extension support.

Language: Verilog - Size: 14.6 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 4 - Forks: 0

Casparvolquardsen/Mikrorechner

Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.

Language: VHDL - Size: 483 KB - Last synced at: 13 days ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 0

farkoo/farkoo-Simulator

An assembler and hardware simulator for Mano Basic Computer, a 16-bit computer.

Language: C# - Size: 262 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 0

vrstanchevLab/ASMLab

Educational resources for learning NASM, GNU ASM, RISC-V assembly language, and C programming. Includes examples, tutorials, and hands-on exercises for mastering low-level systems programming.

Language: Assembly - Size: 318 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 0

UserJHansen/Computer

Custom 32 bit computer

Language: TypeScript - Size: 297 KB - Last synced at: 4 months ago - Pushed at: 11 months ago - Stars: 3 - Forks: 0

marceldobehere/MAAB-CPP-Interpreter

Language: C++ - Size: 357 KB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 0

DivergentClouds/riw-16

A fantasy computer with 16 instructions.

Size: 46.9 KB - Last synced at: 5 months ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

jamestiotio/compstruct

SUTD 2020 50.002 Computation Structures Code Dump

Language: C - Size: 89.7 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

Psmths/riscal-cpu

RISCAL is a 32-bit reduced instruction-set computer (RISC) designed for learning and research purposes. It is named after my dog, Rascal.

Language: C++ - Size: 261 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

arsalanyavari/mano-simulator

An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer

Language: C++ - Size: 69.7 MB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 1

Sacusa/MoCha

A pedagogical processor on FPGA, developed at NIIT University.

Language: VHDL - Size: 798 KB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 3 - Forks: 1

notdroplt/Supernova

Zenith runtime virtual machine

Language: Zig - Size: 154 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 2 - Forks: 0

vrstanchev/Degrees

🎓 M.Sc. in Computer Systems & Technologies 📍 Technical University of Sofia – Plovdiv Branch 🛠️ Specialization: Advanced systems programming, low-level optimizations, Linux internals. 🎓 B.Sc. in Software Engineering 📍 Plovdiv University Paisii Hilendarski

Language: Assembly - Size: 25.3 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

thacuber2a03/float

an attempt at writing a VM

Language: C - Size: 36.1 KB - Last synced at: 3 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 1

JBrosDevelopment/VirtualComputer

This project is a virtual computer that takes a vector of bytes and runs it as instructions. Also included is a complete assembler and compiler.

Language: Rust - Size: 36.4 MB - Last synced at: 4 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 0

HarieshAnbalagan/RV32I

Minimalistic RV32I RISC-V Processor in System Verilog

Language: SystemVerilog - Size: 392 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

fgmn/Computer-Organization-Course-Design

SDU 20级计科计组课设

Language: VHDL - Size: 25.8 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

AshleighAdams/Swis

Simple Wire Instruction Set

Language: C# - Size: 690 KB - Last synced at: 1 day ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

Roninkoi/RAMPE

RAMPE computer ISA with assembler and simulator

Language: Fortran - Size: 289 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

Kirca54/MIPS-Assembly-Instruction

Assembly program

Language: Assembly - Size: 1.95 KB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0

GodTamIt/assembler

A modular general 2-pass assembler written in Python.

Language: Python - Size: 40 KB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

hvudeshi/Context-Switching

Multi-Threaded Simulation of Process Switching in Operating System.

Language: C - Size: 2.9 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 0

anktjsh/Y86-Simulator

Y86 ISA Simulator and Virtual Machine

Language: Java - Size: 2.13 MB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 0

VenkatKS/CHIP8

Full graphical instruction-level emulator for the CHIP-8 Instruction Set Architecture

Language: C - Size: 146 KB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 2 - Forks: 0

zsisco/yaye

yaye is Yet Another y86 Emulator

Language: C - Size: 5.86 KB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 2 - Forks: 0

Mecca-Research/The-Binary-Decomposition-Interface

BDI - A proposed foundational computational substrate, a universal fabric designed to represent any computation.

Language: C++ - Size: 69.1 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1 - Forks: 0

pulkitpareek18/gcc-riscv

This repository contains a fully working GCC cross-compiler toolchain targeting the RISC-V architecture, along with a detailed research paper that provides an overview of Instruction Set Architectures (ISAs), the role of compilers, and the RISC-V compilation flow.

Language: C++ - Size: 10.7 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

adolan527/LC3-RTL

A Verilog implementation of the LC3 (Little Computer 3) micro-architecture/ISA as described in "Introduction to Computing Systems" by Patt & Patel.

Language: Verilog - Size: 13.9 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

HrishikeshSuchindra/Process-In-Memory-ISA-Compiler

📦 PIM Compiler A lightweight compiler for a custom 24-bit Processor-In-Memory (PIM) Instruction Set Architecture. This tool translates simple C-like matrix operations into 24-bit machine instructions through parsing, intermediate representation (IR) generation, and custom microcode mapping.

Language: C - Size: 47.9 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

agicy/buptAsgmt-organization 📦

北京邮电大学 2023-2024 春季学期《计算机组成原理》课程作业的相关文档

Size: 34.7 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

Layheng-Hok/RISC-V-CPU

RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100

Language: VHDL - Size: 25.1 MB - Last synced at: 4 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

jamestiotio/ehp

SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project

Language: Python - Size: 31.5 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Pidova/ISCreator

Create and represent instruction sets in code easily.

Language: C++ - Size: 20.5 KB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

IsaacSteadman/StackVM

A 64-bit stack based instruction set architecture definition with reference implementation. (The assembler is part of my C compiler that targets StackVM)

Language: Python - Size: 142 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

nnk03/PIPELINE-GROUP-13-BATCH-2021-CO-LAB-IIT-PALAKKAD

Pipelining using Verilog done during the Computer Organisation and Architecture Lab during Semester 3

Language: Verilog - Size: 5.45 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

spsandwichman/aphelion16

custom 8/16-bit instruction set architecture

Language: Nim - Size: 487 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

keneoneth/InstrHexBinDecConvertDecoder-Release

a web based front end only helper tool that provides Instruction Decoder and Converter in hexadecimal binary decimal form encoding of different ISA

Language: HTML - Size: 699 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

JohnMachado11/CS104-Computer-Architecture

Python implementation of a 32-bit processor with its own ISA (Instruction Set Architecture)

Language: Python - Size: 13.7 KB - Last synced at: 4 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

patel-soham/16-bit-microprocessor-verilog

A final year undergraduate major project. (Dec 2019 - Mar 2020)

Language: C - Size: 3.06 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

kbecke05/CPE315-Computer-Architecture

A collection of old projects in assembly and Java from class assignments

Language: Java - Size: 58.6 KB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

iaakash47/vsdriscv

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Size: 72.3 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

JiananAlvin/02135_ISA_simulator

This is the implementation of an instruction-set architecture (ISA) simulator in Python. It deals with small machine language programs in order to understand the functionality and the structure of a simple processor.

Language: Python - Size: 861 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

ascordeiro/intrinsics

Intrinsics are high level functions implemented in C language and are based in some ISAs. The mainly purpose is simulate these architectures in SiNUCA (Simulator of Non-Uniforme Caches)..

Language: C++ - Size: 121 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

umvar/JadeVM

The JadeLang Stack-Based Virtual Machine

Language: Assembly - Size: 24.4 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

Benjarit/ECE4270-Computer_Organization

Advanced computer architectures and programming; memory, memory management and cache organizations, parallel processing, graphical processor units for general programming.

Language: C - Size: 1.03 MB - Last synced at: 4 months ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

pradyumnameena/Processor-Design

ARM Multicycle Processor - 32 bit Assembly instructions - VHDL - Arithmetic and Logical operations, Memory read and write - Vivado

Language: VHDL - Size: 325 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 2

danilopeixoto/archer

A simple instruction set architecture.

Language: C++ - Size: 23.4 KB - Last synced at: 2 months ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

nhays89/PC-sim

c assembler & data path simulator implementing the LC-2200 ISA.

Language: C - Size: 1.51 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

8shubham/Smart-Home-Controller

A real time computing machine

Language: C - Size: 3.89 MB - Last synced at: about 1 month ago - Pushed at: almost 8 years ago - Stars: 1 - Forks: 1

yanalex981/6502vm

6502 virtual machine written in C

Language: C - Size: 32.2 KB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

jmcph4/cpu

My attempt at a CPU simulator

Language: C - Size: 5.86 KB - Last synced at: 4 months ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

Nishit-2006/RISC-V-RV32I-Pipelined-Processor-Verilog-Implementation-

Implement a 5-stage pipelined RISC-V RV32I processor in Verilog. Includes a custom Python assembler for easy instruction translation. 🖥️🚀

Language: Verilog - Size: 40.7 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

Simulacrum0/Simulacrum0.github.io

Wantware Deployment Website

Language: HTML - Size: 80.1 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

xxas/mint

C++26 Custom Instruction Set Architecture Framework

Language: C++ - Size: 105 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

Mariuspersen/cisc64

Idea for a new type of architecture

Language: Zig - Size: 71.3 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Alexia022/MIPS_Assembly_Programs

A comprehensive collection of MIPS assembly language programs demonstrating low-level programming concepts, algorithm implementation, and computer architecture principles through practical applications like calculators, pattern generators, and educational tools.

Language: Assembly - Size: 15.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

wyxh2004/c-cpp-learning-snippets

Linux kernel / Algorithm / Instruction Set / Pointer / Makefile / Advanced C Programming

Language: C++ - Size: 155 KB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

ewdlop/Hardware-Notes

Electrical Enignnering

Language: VHDL - Size: 69.8 MB - Last synced at: 2 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

BrandonDao/ProjectISA

A C# assembler, disassembler, and emulator for my custom instruction set architecture (work in progress)

Language: C# - Size: 7.81 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

omrawaley/txt-8

TXT-8 is a simple 8-bit text-based virtual machine with the intent of education on virtualization.

Language: C++ - Size: 43 KB - Last synced at: 5 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

icarogabryel/sea-iv

SEA-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.

Language: Python - Size: 151 KB - Last synced at: 4 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

mehmetakifkoz/MARS-Web-App

This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

Language: JavaScript - Size: 25.4 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0