Topic: "microarchitecture"
OpenXiangShan/XiangShan
Open-source high-performance RISC-V processor
Language: Scala - Size: 34.8 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 6,363 - Forks: 764
google/cpu_features
A cross platform C99 library to get cpu features at runtime.
Language: C++ - Size: 623 KB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 2,517 - Forks: 280
Dr-Noob/cpufetch
Simple yet fancy CPU architecture fetching tool
Language: C - Size: 3.51 MB - Last synced at: 4 days ago - Pushed at: 7 months ago - Stars: 1,985 - Forks: 103
stong/how-to-exploit-a-double-free
How to exploit a double free vulnerability in 2021. Use After Free for Dummies
Language: Python - Size: 18.2 MB - Last synced at: 4 days ago - Pushed at: 4 months ago - Stars: 1,348 - Forks: 65
ShaneK2/inVtero.net
inVtero.net: A high speed (Gbps) Forensics, Memory integrity & assurance. Includes offensive & defensive memory capabilities. Find/Extract processes, hypervisors (including nested) in memory dumps using microarchitechture independent Virtual Machiene Introspection techniques
Language: C# - Size: 88 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 276 - Forks: 57
akhin/microarchitecture-cheatsheet
X86 CPU topics overview for developers , oriented towards performance
Size: 14.1 MB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 196 - Forks: 8
CMU-SAFARI/Pythia
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
Language: C++ - Size: 3.48 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 132 - Forks: 45
HenrikBengtsson/x86-64-level
x86-64-level - Get the x86-64 Microarchitecture Level on the Current Machine
Language: Shell - Size: 55.7 KB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 112 - Forks: 16
Jerc007/Open-GPGPU-FlexGrip-
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
Language: VHDL - Size: 4.57 MB - Last synced at: 27 days ago - Pushed at: about 2 years ago - Stars: 99 - Forks: 19
ucb-bar/saturn-vectors
Chisel RISC-V Vector 1.0 Implementation
Language: Assembly - Size: 54.1 MB - Last synced at: about 1 hour ago - Pushed at: 11 days ago - Stars: 97 - Forks: 10
codexlynx/hardware-attacks-state-of-the-art
Microarchitectural exploitation and other hardware attacks.
Size: 189 KB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 85 - Forks: 11
Dr-Noob/peakperf
Achieve peak performance on x86 CPUs and NVIDIA GPUs
Language: C++ - Size: 250 KB - Last synced at: 28 days ago - Pushed at: 7 months ago - Stars: 69 - Forks: 15
CMU-SAFARI/Hermes
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
Language: C++ - Size: 4.53 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 65 - Forks: 12
libtea/frameworks
Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
Language: C - Size: 251 KB - Last synced at: 29 days ago - Pushed at: almost 3 years ago - Stars: 61 - Forks: 18
jiegec/cpu-micro-benchmarks
CPU micro benchmarks
Language: Assembly - Size: 4.46 MB - Last synced at: 27 days ago - Pushed at: about 2 months ago - Stars: 55 - Forks: 3
k-nuth/kth
High performance Bitcoin development platform
Language: Python - Size: 3.02 MB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 30 - Forks: 6
vhive-serverless/vSwarm-u
Framework that integrates the serverless benchmark suite vSwarm with gem5, the state-of-the-art research platform for system-and microarchitecture.
Language: Python - Size: 13.9 MB - Last synced at: 20 days ago - Pushed at: about 1 month ago - Stars: 28 - Forks: 6
dhschall/gem5-fdp Fork of gem5/gem5
Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
Language: C++ - Size: 266 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 19 - Forks: 3
b-shi/PMC-PMI
Performance Counter Measurements at the cycle granularity
Language: C - Size: 161 KB - Last synced at: 7 months ago - Pushed at: almost 4 years ago - Stars: 17 - Forks: 3
kuby1412/RISC-V-MYTH-Workshop
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
Language: C - Size: 7.51 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 16 - Forks: 1
yonseicasl/Kite
Kite: Architecture Simulator for RISC-V Instruction Set
Language: C++ - Size: 2.82 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 14 - Forks: 5
AliLRS/RISC-V_Microprogrammed
Language: SystemVerilog - Size: 470 KB - Last synced at: 10 months ago - Pushed at: almost 2 years ago - Stars: 14 - Forks: 1
FISC-Project/FISC-VHDL
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
Language: VHDL - Size: 111 MB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 4
toor1245/cpu_features.NET
.NET version of google/cpu_features to get cpu info at runtime.
Language: C# - Size: 342 KB - Last synced at: 5 months ago - Pushed at: 9 months ago - Stars: 13 - Forks: 2
dominiksalvet/risc63
Custom 64-bit pipelined RISC processor
Language: VHDL - Size: 421 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 13 - Forks: 1
mamadaliev/sequent
Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog
Language: Verilog - Size: 7.81 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 10 - Forks: 1
aecsocket/cpu-features-java
Java bindings for Google cpu_features
Language: Java - Size: 374 KB - Last synced at: about 1 month ago - Pushed at: 11 months ago - Stars: 9 - Forks: 1
saintube/gem5-dscp 📦
DSCP is a dynamic secure cache partitioning implementation on gem5. The code includes a ScatterCache (USENIX SECURITY'19) variant and it is partially available to reproduce set partitioning.
Language: C++ - Size: 226 MB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 9 - Forks: 1
evanlissoos/OISC
One Instruction Set Computer
Language: Python - Size: 212 KB - Last synced at: 6 months ago - Pushed at: almost 8 years ago - Stars: 9 - Forks: 2
dominiksalvet/limen-alpha
Dual-core 16-bit RISC processor
Language: VHDL - Size: 700 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 8 - Forks: 2
dominiksalvet/super-riscv
Superscalar dual-issue RISC-V processor
Language: SystemVerilog - Size: 1.78 MB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 7 - Forks: 3
CMU-SAFARI/Load-Inspector
A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arxiv.org/pdf/2406.18786
Language: C++ - Size: 243 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 7 - Forks: 1
halworsen/gem5-runahead
A runahead execution CPU model in the gem5 simulator - feat. delayed exit experiments
Language: C++ - Size: 819 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 0
hoseinyavarzadeh/archsec-deadlines Fork of paperswithcode/ai-deadlines
:alarm_clock: Computer Architecture and Security Conference Deadline Countdowns (Based on AI Deadlines)
Language: JavaScript - Size: 1.38 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 5 - Forks: 0
lywangj/Modelling_Apple_M1_CPU_Architecture
2021-22 Summer Project in Computer Science
Language: Assembly - Size: 1.78 MB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1
leepoly/chisel-pobu-cache
Language: Verilog - Size: 709 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 0
EngineersBox/GBox16-GPU
Implementation of a custom GPU ISA microarchitecture called GBox16 based around NVIDIA and AMD microarchitectures
Language: VHDL - Size: 611 KB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 4 - Forks: 0
Sacusa/LC-3 📦
An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".
Language: VHDL - Size: 22.5 KB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 4 - Forks: 4
Kingfish404/ysyx-workbench
OoO 6-stage RISC-V core. Verify: riscv-arch-test-am. Difftest: Spike & NEMU (boot Linux).
Language: C - Size: 5.74 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 3 - Forks: 0
yuri-panchul/tt08-adder-with-flow-control Fork of TinyTapeout/tt08-verilog-template
Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.
Language: SystemVerilog - Size: 43.9 KB - Last synced at: 8 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 1
grachale/microarchitecture_RISC_V
Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.
Language: Verilog - Size: 86.9 KB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0
dominiksalvet/tine-alpha
8-bit MISC processor with pipelining
Language: VHDL - Size: 470 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 2
hushon/Tiny-RISCV-CPU
Mini RISC-V CPU
Language: Verilog - Size: 143 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 2
jasha64/ARM9-compatible-soft-CPU-core
an ARM9 compatible CPU core written in Verilog, and related experiments
Language: VHDL - Size: 13.8 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 2
MIPT-ILab/MDSP 📦
[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor
Language: C++ - Size: 23.1 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 1
Sacusa/MoCha
A pedagogical processor on FPGA, developed at NIIT University.
Language: VHDL - Size: 798 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 1
tommythorn/multisim
MultiSim is Yet Another CPU Simulator which purpose in life is to allow easy experimentation with various implementation strategies, such as superscalar in-order, sscalar out-of-order, speculative sscalar out-of-order, etc.
Language: C - Size: 35.5 MB - Last synced at: 5 days ago - Pushed at: 6 months ago - Stars: 2 - Forks: 0
Naminar/tlb-v
Simple TLB (Translation lookaside buffer) realization on verilog.
Language: Verilog - Size: 2.24 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 1
EngineersBox/CBox16-Processor
Implementation of QuAC v1.0 ISA microarchitecture called CBox16
Language: VHDL - Size: 1.45 MB - Last synced at: about 2 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 0
dominiksalvet/limen
16-bit RISC processor with von Neumann architecture
Language: VHDL - Size: 53.7 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 1
dominiksalvet/pcycle
My first processor written in HDL language
Language: VHDL - Size: 200 KB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2
dominiksalvet/six-alpha
Accumulator-based 4-bit processor
Language: VHDL - Size: 268 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0
Amir-Shamsi/MIPS-Microarchitecture-Processor
MIPS Single-Cycle Microarchitecture Processor
Language: Java - Size: 75.2 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0
filipecosta90/redismodule-sample-cpu-features
A cross platform Redis Module Example that warns and uses the optimized functions based on instruction set extensions available and or microarchitecture
Language: C - Size: 14.6 KB - Last synced at: about 2 months ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0
adolan527/LC3-RTL
A Verilog implementation of the LC3 (Little Computer 3) micro-architecture/ISA as described in "Introduction to Computing Systems" by Patt & Patel.
Language: Verilog - Size: 13.2 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0
pwintz/sharc
Simulator for Hardware Architecture and Real-time Control
Language: C++ - Size: 1.42 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0
joshtynjala/cairngorm
Archive of the Cairngorm framework version 2 for Adobe Flex
Language: ActionScript - Size: 934 KB - Last synced at: 4 days ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0
Mvk122/UOM-CompSci-Notes
My notes from the computer science course at The University of Manchester.
Size: 44.2 MB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
noriaku/multicycle-arm
Implementation of multicycle microarchitecture for arm processor with extended functionalities using verilog programming language.
Language: Verilog - Size: 635 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
jaydinandrews/llama-16
16-bit microarchitecture with a custom instruction set, assembler, and emulator.
Language: TeX - Size: 533 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
tommythorn/bp
Fun with branch predictors
Language: Rust - Size: 28.3 KB - Last synced at: 5 days ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
sayeekumar332/PROCESSOR-MICROARCHITECTURE
This is a repository exclusively created for providing open source verilog codes for various processor microarchitectures and various programming language based codes for research purpose
Language: Verilog - Size: 251 KB - Last synced at: 12 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
Scrawach/riscv
Pipelined CPU microarchitecture RISC-V ISA RV32I.
Language: Verilog - Size: 1.15 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 1
AnsgarKlein/x86-feature-check
Checker for x86-64 feature sets
Language: Python - Size: 90.8 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1
saruman9/micro_arch_side_channel_attacks_pres
Presentation about software-based Micro-architectural Side-Channel attacks.
Language: TeX - Size: 9.03 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
bengras/tlbkit
some tlb experimentation code: calculate L1, L2 miss penalties and show cross-HT interference.
Language: Python - Size: 96.7 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1
maazm007/riscv-myth-core
This repository contains the design of RISC-V CPU 5-staged Core
Language: Verilog - Size: 6.18 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
HadrienG2/subwoofer
Assessing the impact of subnormals on your CPU's performance
Language: Rust - Size: 558 KB - Last synced at: 4 days ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
i3abghany/Rx32
Fine-grained multithreaded, software-interlocked core in RISC SystemVerilog.
Language: C - Size: 531 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
PhuwadonV/AsmMeasure
Learning x86-64 microarchitecture through analyzing data measured by assembly language.
Language: Assembly - Size: 52.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
MSK61/processorsim
program execution simulator on processors
Language: Python - Size: 2.14 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
DavidMorano/research
high instruction-level-parallelism (ILP) using Resource-Flow-Execution
Language: C - Size: 48.9 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
thewillyan/vondel
A simple computer architeture, ISA and Interpreter build with Rust.
Language: Rust - Size: 1.55 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
salekinsirajus/721-sim-renamer
Class project for ECE721: Advanced Microarchitecture. This project involves implementing a renamer class that uses AMT, RMT, Active List, Free List, and Physical Register File.
Language: C++ - Size: 591 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
xor50/MALconverter
small program to convert Micro Assembly Language lines to binary microinstruction code for the Mic-1 and to hex for use in Logisim
Language: Java - Size: 18.6 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
leonardonps/projetos-finais-arquitetura-de-computadores
Projetos finais realizados durante a disciplina de Arquitetura de Computadores.
Language: Assembly - Size: 1.32 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
lucamodica/computer-architecture-exercises--bachelor
Bunch of excercises about IJVM language (JVM ISA language only on integers) and MAL microcode for new istruction implementations, in Mic-1 architecture.
Size: 2.41 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
rickydebojeet/Cache-Detector
Find cache of your computer!!
Language: C - Size: 36.7 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
noncombatant/absolutelynot.computer
A bibliography of hardware vulnerabilities.
Language: HTML - Size: 13.7 KB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
aj-staton/u-architecture
32-bit RISC-V microarchitecture with a three-stage pipeline
Language: C - Size: 1.74 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
MIPT-ILab/PipelineVis Fork of AlexK168/CourseProject2020 📦
CPU Pipeline Visualization Tool
Language: C++ - Size: 19.5 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
naftali10/Single-Cycle-MIPS
A System Verilog processor design of a single cycle MIPS architecture
Language: SystemVerilog - Size: 54.7 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
aronsonj52/riscv_myth_workshop
riscv_myth_workshop created by GitHub Classroom. Contains an implemented RISC-V 32-bit core.
Language: Coq - Size: 2.04 MB - Last synced at: 11 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
GeoBK/721sim
Implements a BDP (Branch difference predictor) based on the paper by Timothy H Heil, Zak Smith and JE Smith - "Improving branch predictors by correlating on data values"
Language: C++ - Size: 531 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0
zhuangsc/RFC_marss86
Register file cache implementation on the Marssx86 architectural simulator
Language: C - Size: 14.2 MB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0
