arm-university/Introduction-to-Computer-Architecture-Education-Kit

Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors

Language: HTML - Size: 31.5 MB - Last synced at: 16 days ago - Pushed at: 9 months ago - Stars: 270 - Forks: 47

alirezakay/RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Language: VHDL - Size: 2.52 MB - Last synced at: about 1 month ago - Pushed at: almost 4 years ago - Stars: 27 - Forks: 5

RossComputerGuy/SherwoodArch

The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.

Language: CSS - Size: 1.17 MB - Last synced at: 4 days ago - Pushed at: over 6 years ago - Stars: 15 - Forks: 1

MaorAssayag/Architecture-of-CPU-projects

VHDL , ModelSIM, Quartus, FPGA, Image Processing

Language: VHDL - Size: 128 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 14 - Forks: 3

lolguy91/SCAP 📦

the Stupidest CPU Arch Possible

Language: C - Size: 545 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 4 - Forks: 1

MIPT-ILab/MDSP 📦

[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor

Language: C++ - Size: 23.1 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 1

schemil053/ScheCPUEmulator

This is a simple CPU emulator with custom architecture

Language: Java - Size: 172 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 1

amari-calipso/custom-emulated-computer

A 16-bit computer architecture i made, emulated in opal

Language: Opal - Size: 192 KB - Last synced at: 17 days ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

codehasan/MyArch

📱 An app to view all supported ABI of the running device

Language: Java - Size: 857 KB - Last synced at: 5 days ago - Pushed at: 8 months ago - Stars: 2 - Forks: 1

eomielan/16-bit-RISC-machine

16-bit CPU architecture implementation and verification using SystemVerilog

Size: 179 KB - Last synced at: 2 months ago - Pushed at: 8 months ago - Stars: 2 - Forks: 0

JimCownie/CpuFun

Code snippets for the CpuFun blog

Language: C++ - Size: 78.1 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

uros-bojanic/8-bit-computer

[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.

Size: 3.19 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

Kammann123/ev21g1

General purpose processor with a RISC architecture and a five stage pipeline, implemented on a Cyclone IV FPGA using a development board

Language: Verilog - Size: 8.45 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 2

MartinBrugnara/archetypum

Tomasulo algorithm visualizer

Language: TypeScript - Size: 254 KB - Last synced at: 2 months ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 0

MEESAM749/Single-Cycle-Non-Pipelined-MIPS-32-Processor

This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.

Language: C - Size: 1.97 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 1 - Forks: 0

MEESAM749/RISC-V-PipelinedProcessor

RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE

Language: HTML - Size: 602 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 1 - Forks: 0

oceanwebturk/ankaosx

OceanWebTurk AnkaOS X

Language: C - Size: 30.3 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

onegentig/VUT-FIT-INP2022-projekt1 📦

První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Language: VHDL - Size: 2.42 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

SexySparrow/RISC_V

RISC-V CPU arhitecture

Language: Verilog - Size: 10.7 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

ewpratten/Dirobium 📦

The virtual CPU (and emulator) built for hobbyists

Language: Python - Size: 70.3 KB - Last synced at: 12 months ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

denishoornaert/SimpleSoftcoreArchitecture

Language: VHDL - Size: 815 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

Mariuspersen/cisc64

Idea for a new type of architecture

Language: Zig - Size: 71.3 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 0 - Forks: 0

Haaris-RTL/8-bit-CPU

RTL code of an 8-bit CPU designed in Verilog.

Language: Verilog - Size: 97.7 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 1

simon-gardier/cpu-design

📟 32 bits CPU design

Language: Python - Size: 6.1 MB - Last synced at: about 1 month ago - Pushed at: 11 months ago - Stars: 0 - Forks: 1

Hridxyz/Microprocessor-Assembly-Language

A repository of my assembly language learning journey, featuring programs that illustrate the core principles of microprocessor operations and low-level coding.

Language: Assembly - Size: 211 KB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1

Sayemum/CS261-Y86-CPU-Simulator

My semester-long project for CS261 - Computer Systems at James Madison University where I constructed a cpu simulator using a smaller version of x86 called y86.

Language: C - Size: 81.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

garrettknuf/Caltech10-CPU

8-bit Harvard Architecture CPU implemented in ABEL

Size: 175 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ThiagoDSMarcelino/cpu-architecture 📦

16-bit CPU with specific Assembler for Assembly codes capable of controlling a 32x32 led screen

Language: C# - Size: 29.3 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

srki/RISC-V-Simulator

Assembler and Simulator for RISC-V RV32I instruction set that runs entirely in web browser.

Language: TypeScript - Size: 8.46 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

erwanregy/NoC-Simulation

Network-on-Chip Simulation using Noxim

Language: Python - Size: 22.5 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

mohdfahad12328/scpu

a smiple 8bit cpu implemented in verilog and tested on FPGA for understanding how CPU works

Language: Verilog - Size: 1.77 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

erwanregy/Cache-Simulation

CPU Cache Simulation using gem5

Language: C - Size: 34.5 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

cedrickchee/nand2tetris

Solutions for http://www.nand2tetris.org/

Language: Hack - Size: 475 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

ParkerTenBroeck/MyCPU_16bit

A 16 bit SAP-1 CPU that I designed in grade 10 designed in logisim

Size: 6.48 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

TotoroTron/495_CPU

A simple 8-bit CPU.

Language: VHDL - Size: 242 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

almidi/VHDL_Charis_4

Basic VHDL projects gradually creating a pipelined CPU running Charis4 instruction set.

Language: C - Size: 8.14 MB - Last synced at: 6 months ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 1

Zardoz89/trillek-computer Fork of trillek-team/trillek-computer

Trillek Virtual Computer specs

Language: HTML - Size: 3.45 MB - Last synced at: about 2 years ago - Pushed at: almost 10 years ago - Stars: 0 - Forks: 0