Topic: "single-cycle-processor"
martinKindall/risc-v-single-cycle
A Single Cycle Risc-V 32 bit CPU
Language: SystemVerilog - Size: 36.1 KB - Last synced at: 4 months ago - Pushed at: over 2 years ago - Stars: 38 - Forks: 2
aofarmakis/Nibbling-bits
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
Language: Verilog - Size: 4.01 MB - Last synced at: 4 months ago - Pushed at: 8 months ago - Stars: 32 - Forks: 0
phillbush/legv8
LEGv8 CPU implementation and some tools like a LEGv8 assembler
Language: Verilog - Size: 124 KB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 29 - Forks: 6
martinKindall/mips_cpu
Single Cycle 32 bit MIPS
Language: SystemVerilog - Size: 280 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 20 - Forks: 1
samadpls/ALEPH
Aleph is a single cycle processor that carries out one instruction in a single clock cycle
Language: Scala - Size: 37.2 MB - Last synced at: 4 months ago - Pushed at: almost 2 years ago - Stars: 6 - Forks: 0
arsalanjabbari/MIPS-CPU-Design
This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.
Language: Verilog - Size: 8.79 KB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 5 - Forks: 0
explcre/21Summer-VE370-Intro-to-Computer-Organization-Projects
21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.
Language: Verilog - Size: 11.6 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 0
JoyenBenitto/grape
grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.
Language: SystemVerilog - Size: 196 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 4 - Forks: 1
Prajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
Language: Tcl - Size: 146 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 1
muhammadtalhasami/RV32I_Single_Cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
Language: Verilog - Size: 168 KB - Last synced at: 3 months ago - Pushed at: 12 months ago - Stars: 3 - Forks: 0
Vedant2311/Complete-ARM-CPU
Single and Multi-cycle ARM processors implemented using VHDL
Language: VHDL - Size: 354 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
hwlabnitc/hwlabnitc.github.io
Main website of the HW Lab guide by NITC
Size: 24.6 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 4
Asterinos1/Neighbour-s-CPU-v2
This rep contains neighbour's cpu. Single-cycle / Multi-cycle CPU implementation in vhdl using ISE Xiling
Language: VHDL - Size: 5.96 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 2 - Forks: 0
muhammadtalhasami/rv32I_single_cycle_logisim
An implementation of rv32i single cycle processor on logisim
Size: 149 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1
kamplianitis/SingleCycleProcessor
Single cycle processor Design for the purposes of the course Computer Organisation at Technical University of Crete (TUC)
Language: VHDL - Size: 261 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 2
PebPeb/Single-Cycle-RV32I
Single Cycle CPU using the RV32I Base Instruction set
Language: Verilog - Size: 3.2 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0
Visheshanagu2894/riscv
RISC-V 32IM - Dobby SOC
Language: Verilog - Size: 2.38 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
OmarAmer01/VP_Harvard_MIPS
A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.
Language: Verilog - Size: 33.9 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 2
Amir-Shamsi/MIPS-Microarchitecture-Processor
MIPS Single-Cycle Microarchitecture Processor
Language: Java - Size: 75.2 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0
Elzawawy/mips-processor-simulator
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
Language: SystemVerilog - Size: 1.05 MB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 3
jawwad9921iu39/Single-Cycle-Processor
This repository contains code for Single Cycle rv32i Processor.
Language: Verilog - Size: 637 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 1 - Forks: 0
bruno-andrade3/mips32VHDL
MIPS 32 VHDL Project
Language: VHDL - Size: 2.33 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0
ntsdwkr/MIPS
Single Cycle MIPS (RISC) Processor
Language: Verilog - Size: 1.09 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
FareedCodess/Single_Cycle_CPU
This project showcases the design of a single cycle central processing unit which was built using the logisim.
Size: 670 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
MUST-SCSE-SE-2018/Single-Cycle-Processor
đź’» The project of MUST CO101 Computer Organization
Language: C - Size: 180 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
Whitelisted2/CS311-CompArch-Lab
This repository contains files related to Computer Architecture Lab (Autumn 2022).
Language: Java - Size: 14.1 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1
viraj-dhanushka/Verilog-based-CPU
A 32-bit CPU which includes an ALU, a Register File, Control Unit, Data and Instruction memory
Language: Verilog - Size: 876 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 1
kalhorghazal/Mips-SingleCycle
Mips Single-Cycle, Computer Architecture course, University of Tehran
Language: SystemVerilog - Size: 21.5 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0
MaheenAnees/Single-Cycle-RISCV-Processor
This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.
Language: Verilog - Size: 8.79 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
Awais-Asghar/Single-Cycle-RISC-V-Processor-Implemented-on-FPGA
An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.
Language: SystemVerilog - Size: 38.1 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0
Karrs725/NYCU-S23-COLab
Assignments for Computer Organization (Undergraduate Course, NYCU)
Language: Verilog - Size: 4.01 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
LiPtP0000/CPU_Design
16-bit single-cycle CPU using Verilog
Language: TeX - Size: 62.9 MB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
Arsham-LH/Computer-Architecture
Code files related to the Computer Architecture course, taught by M. Movahedin
Language: Verilog - Size: 593 KB - Last synced at: 5 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
VesalBargi/verilog-single-cycle-cpu
A ModelSim project that implements a MIPS single-cycle CPU using Verilog.
Language: Verilog - Size: 241 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
pai4451/Single-Cycle-MIPS-CPU
Single Cycle 32 bits MIPS CPU
Language: Verilog - Size: 1.57 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
codingwthisa/Procesador-Monociclo-RISCV
ImplementaciĂłn del procesador monociclo RISC-V en System Verilog.
Language: SystemVerilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Ammar-Bin-Amir/RV32I_5-Stage_Pipelined_CPU
Processor Design of RV32I 5-Stage Pipelined CPU
Language: SystemVerilog - Size: 170 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Ammar-Bin-Amir/RV32I_Single_Cycle_CPU
Processor Design of RV32I Single Cycle CPU
Language: SystemVerilog - Size: 590 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
RicardoATT/Procesador_monociclo
RISC-V single-cycle processor written in Verilog using the Quartus tool. Implementation of bubble sort through assembly language.
Language: Tcl - Size: 56.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Engineer-Ayesha-Shafique/RISC-V-Single-Cycle-Processor
This is a Single Cycle processor running the RV32I implementation, hence a 32-bit CPU, written in SystemVerilog.
Language: SystemVerilog - Size: 8.54 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
MarleyLobao/Single-Cycle_MIPS_Processor
This repository holds files related to the development of a Single-Cycle Processor developed during the Digital Systems Architecture course.
Language: Verilog - Size: 27.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
JavidChaji/FUM-Computer-Architecture-Single-Cycle-MIPS-Processor
Single Cycle MIPS Processor implementation, Computer Assignment for Computer Architecture course in Ferdowsi University of Mashhad
Language: Verilog - Size: 728 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
alighanbari2002/MIPS-Processor Fork of M-Mashreghi/MIPS
MIPS processor designed in Verilog.
Language: Verilog - Size: 9.69 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
alighanbari2002/Computer-Architecture-Course-Projects Fork of M-Mashreghi/Computer-Architecture
All Computer Architecture course projects offered at University of Tehran.
Language: Verilog - Size: 14.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
Riyadhz20/COA_Project
Design using Logisim to make a Single-Cycle 32-Bit CPU for a subset of the MIPS instructions
Size: 220 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
algorhtym/mips-single-cycle-processor
A digital design project for a MIPS Reduced Instruction Set Computer (RISC) single-cycle processor design that supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL
Language: VHDL - Size: 12.7 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
sts08015/risc-v-lab
Extended Version of COSE222 Lab
Language: SystemVerilog - Size: 59.6 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
juliocesarlq/Single-Cycle-MIPS-CPU
design a single-cycle MIPS CPU in C++. Single-cycle CPU program needs to be able to execute the following 10 instructions LW, SW, ADD, SUB, AND, OR, SLT, NOR, BEQ, J.
Language: C++ - Size: 658 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
haowoo0112/Single-Cycle-RISC-Verilog
Language: C - Size: 1.98 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
iamazizhaider/singlecycle_riscv_processor
This project was designed to run on Nexys A7 Artix-7 FPGA Trainer Board. This processor written in System Verilog can run I-Type, R-Type, B-Type, S-Type RISC-V commands. The current instruction set that has been uploaded here finds the greatest common divisor of two numbers.
Language: SystemVerilog - Size: 18.6 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
Athanasioschourlias/Mips-single-cycle
This is a simple implementation of the MIPS single cycle processor that is described and taught in the book of "Computer Organisation and Design" from Patterson and Hennessy.
Language: Verilog - Size: 15.6 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
albertovallef/MIPS-Simulator
Supports 12 MIPS instructions
Language: C++ - Size: 191 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0
petroud/SingleCycleProcessor
Single Cycle Processor with an ISA like MIPS x32 implemented in VHDL.
Language: VHDL - Size: 2.9 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
kalhorghazal/Computer-Architecture-Course-Projects
👷‍♀️Computer Architecture Course Projects, University of Tehran
Size: 1.95 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0
mohammadasim98/MIPS-Pipeline-Processor
A single cycle pipeline processor based on MIPS instruction set architecture (ISA)
Language: C - Size: 4.35 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0
jpvp13/CSE140_Project
Spring 2021 UCM CSE140 (Single-cycle MIPS CPU) & (Pipelined MIPS CPU)
Language: C - Size: 323 KB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
esteban-gasan/single-cycle-processor
A Verilog implementation of a single cycle processor using the LEGv8 instruction set architecture
Language: Verilog - Size: 24.4 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
sarthak-chakraborty/KGPRISC
Single Cycle CPU design (RISC architecture) developed in Xilinx ISE 14.7 using Verilog
Language: Verilog - Size: 851 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0
