GitHub / JoyenBenitto / grape
grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JoyenBenitto%2Fgrape
PURL: pkg:github/JoyenBenitto/grape
Stars: 4
Forks: 1
Open issues: 2
License: bsd-3-clause
Language: SystemVerilog
Size: 196 KB
Dependencies parsed at: Pending
Created at: almost 2 years ago
Updated at: over 1 year ago
Pushed at: over 1 year ago
Last synced at: over 1 year ago
Topics: risc-v, riscv32, single-cycle-processor, systemverilog