pipelined-processors | Topic | Ecosyste.ms: Repos

Topic: "pipelined-processors"

ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

Language: Verilog - Size: 2.98 MB - Last synced at: 19 days ago - Pushed at: over 3 years ago - Stars: 980 - Forks: 164

JunnanLi/NanoCore

A Pipelined RISC-V Core

Language: Verilog - Size: 13.6 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 8 - Forks: 1

ZeyadTarekk/RISC-Pipelined-Processor

5 stages RISC pipelined processor following Harvard architecture.

Language: Verilog - Size: 666 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 3

Matrixpecker/VE370-Pipelined-Processor

An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.

Language: Verilog - Size: 1.44 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 1

fardinabbasi/RISC-V_Processor_Pipelined

Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

Language: Verilog - Size: 883 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 6 - Forks: 1

Sanskar777/Dynamic-branch-predictor-in-pipelined-processors

Language: Verilog - Size: 253 KB - Last synced at: 2 months ago - Pushed at: over 5 years ago - Stars: 6 - Forks: 1

abdullahalshawafi/RISC-Processor

A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA. There are eight 2-byte general-purpose registers, and another three special-purpose registers (Program Counter, Exception Program Counter, Stack Pointer). The memory address space is 1 MB of 16-bit width and is word addressable.

Language: VHDL - Size: 556 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 3

EmanOthman21/MIPS-Pipelined-Processor

This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.

Language: VHDL - Size: 396 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 1

helcsnewsxd/famaf-computer_science-computer_architecture 📦

Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

Language: SystemVerilog - Size: 6.83 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

helcsnewsxd/famaf-computer_science-computer_architecture-lab2 📦

Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

Language: Assembly - Size: 1.85 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

naderabdalghani/32-bit-risc-pipelined-processor

Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python

Language: VHDL - Size: 18.1 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 4

Elzawawy/mips-processor-simulator

A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.

Language: SystemVerilog - Size: 1.05 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 3

Cambrian34/Cs-385-Semester-Project

16-bit 5 stage pipelined Mips processor

Language: Verilog - Size: 4.88 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

AhsanAliUet/riscv-3-stage-pipelined-processor-core

Fully implemented 3 staged pipelined RISC-V processor with hazard detection unit. Hazard detection unit solves the hazards by stalling and forwarding technique. CSR and MRET Instructions are also supported as they can configure and manage all the interrupt/exceptions.

Language: SystemVerilog - Size: 40.4 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

AbdelrahmanHamdyy/RISC-Pipelined-Processor Fork of SarahElzayat/RISC-pipelined-processor

5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.

Size: 10.8 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

ce-box/CE4302-vector-processor

Vector ASIP for the application of filters to an image 🖼️

Language: SystemVerilog - Size: 56 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

akankshac-073/MIPS-5-stage-pipelined-control-and-datapath

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.

Language: Verilog - Size: 20.5 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 1

MaheenAnees/Single-Cycle-RISCV-Processor

This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.

Language: Verilog - Size: 8.79 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

abdulkhan94/Computer-Design-and-Prototyping

MIPS 32 bit processor - fully functional shared memory dual-core processor with MSI for cache coherency

Language: SystemVerilog - Size: 2.16 MB - Last synced at: over 1 year ago - Pushed at: almost 8 years ago - Stars: 1 - Forks: 0

francoriba/MIPSPipeline

Repository for development of lab3

Language: Verilog - Size: 29.2 MB - Last synced at: 30 days ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

meeeeet/5-Stage-Pipelined-RISC-V-Processor

Language: Verilog - Size: 4.59 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

anyakara/mips32-processor

High-level block designs for MIPS 32 bit processor with pipelining & forwarding controls, hazard detection, and timing. Tested and verified in EECS 112L course on Organization of Computers.

Language: Verilog - Size: 14.5 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

sts08015/risc-v-lab

Extended Version of COSE222 Lab

Language: SystemVerilog - Size: 59.6 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

DoniaGameel/Pipelined-Processor-using-verilog

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor

Language: Verilog - Size: 891 KB - Last synced at: 17 days ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

avikram2/RISCVPipelinedProcessor

Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.

Language: Verilog - Size: 2.48 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0