Topic: "set-associative-cache"
tugrul512bit/LruClockCache
A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.
Language: C++ - Size: 456 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 54 - Forks: 5
yadav-sachin/Multilevel-Cache-Controller
Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy. Implemented on a Basys3 Artix-7 FPGA with proper delays and hit signals.
Language: Verilog - Size: 13.8 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 0
Swap76/Cache_Mapping_Technique
Simulator for Direct, Associative, Set Associative Mapping Technique in Cache Allocation
Language: C++ - Size: 28.3 KB - Last synced at: 18 days ago - Pushed at: over 5 years ago - Stars: 5 - Forks: 1
paulmooreparks/SetAssociativeCache
C# implementation of a set-associative cache with multiple policies (LRU, LFU, etc.)
Language: C# - Size: 880 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1
niksram/Cache-Mapping-Simulator
The following program here helps in simulating how blocks from main memory can get mapped to cache based on strategies: Direct-Mapping, Fully-Associative, Set-Associative
Language: C++ - Size: 23.1 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 1
franciscofpereira/DualCacheSimulator
Dual hierarchy (L1 and L2) cache simulator with direct mapping and two way associative configurations. Project for Computer Organization class.
Language: C - Size: 340 KB - Last synced at: 28 days ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0
rgongw0414/Set-Associative-Cache
Simulation of Set Associative Cache
Language: Python - Size: 341 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
avikram2/RISCVPipelinedProcessor
Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
Language: Verilog - Size: 2.48 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
0mega28/TLB-Controller
2-level TLB Controller
Language: C++ - Size: 286 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
poofypigeon/cache-controller
Fully parametric Set Associated Cache with a Pseudo Least Recently Used replacement policy implemented in VHDL.
Language: VHDL - Size: 107 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0
GSri30/CacheImplementation
A simple implementation of a Direct Mapped Cache and Set Associative Cache in C++. Supports for different sizes of the cache, block, #ways, etc.
Language: C++ - Size: 3.26 MB - Last synced at: about 2 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
