Topic: "out-of-order"
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language: Scala - Size: 53.3 MB - Last synced at: 1 day ago - Pushed at: 2 days ago - Stars: 1,822 - Forks: 700
RRZE-HPC/OSACA
Open Source Architecture Code Analyzer
Language: Jupyter Notebook - Size: 8.15 MB - Last synced at: 7 days ago - Pushed at: 10 days ago - Stars: 319 - Forks: 21
mathis-s/SoomRV
A simple superscalar out-of-order RISC-V microprocessor
Language: SystemVerilog - Size: 11.7 MB - Last synced at: 6 days ago - Pushed at: 2 months ago - Stars: 202 - Forks: 16
riscv-software-src/riscv-perf-model
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Language: C++ - Size: 2.05 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 163 - Forks: 67
sifferman/labs-with-cva6
Advanced Architecture Labs with CVA6
Language: SystemVerilog - Size: 311 KB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 58 - Forks: 26
bcrafton/processor
A compiler, assembler, and processor.
Language: OCaml - Size: 523 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 24 - Forks: 5
SIMDE-ULL/SIMDE
Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals
Language: TypeScript - Size: 11.3 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 13 - Forks: 10
NOP-Processor/NOP-Core
High performace LA32R out-of-order processor core. (NSCSCC 2023 特等奖)
Language: Scala - Size: 21 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 13 - Forks: 0
RISMicroDevices/RMM4NC30F2X 📦
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
Language: VHDL - Size: 31.3 MB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 9 - Forks: 1
RISMicroDevices/RMR8PM3001A
Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC
Language: C++ - Size: 557 KB - Last synced at: 14 days ago - Pushed at: almost 3 years ago - Stars: 9 - Forks: 1
DataSystemsGroupUT/Adaptive-Watermarks
An approach to apply concept drifts and ADWIN on the streams event time to reason about the progress of watermarks
Language: Java - Size: 527 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 9 - Forks: 0
CSpyridakis/Tomasulo 📦
Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm
Language: VHDL - Size: 8.29 MB - Last synced at: 4 days ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 1
TawfikYasser/Keyed-Watermarks-in-Apache-Flink
Keyed Watermarks in Apache Flink
Language: Java - Size: 509 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 3 - Forks: 1
wh1t3h47/EdgeMailer
EdgeMailer is a tool that tests rate limits of mail providers, it uses libcurl and libuv to make concomitant assynchronous request. This tool is outdated and now is closed source and belongs to YouSendr.
Language: C - Size: 22.5 KB - Last synced at: 22 days ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
mark-i-m/riscy 📦
Superscalar OoO RISCV processor written in Chisel
Language: Scala - Size: 9.14 MB - Last synced at: 5 months ago - Pushed at: over 8 years ago - Stars: 3 - Forks: 2
AyuubMohamud/Biriq
2-way Out of Order RISC-V Processor
Language: C - Size: 1.31 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 2 - Forks: 0
helcsnewsxd/famaf-computer_science-computer_architecture-lab2 📦
Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Language: Assembly - Size: 1.85 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0
noionion/KaiSui
try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor
Language: Verilog - Size: 254 KB - Last synced at: 5 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0
agarwal-ayushi/HPC_Labs
This repository contains the Labs done in the course COL718 High Performance Computing taught by Prof. Sourav Bansal at IIT, Delhi in Fall 2019
Language: C++ - Size: 2.5 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0
wdamron/bitring
Go implementation of a bitmap ring-buffer which tracks the state of windowed out-of-order processing over a sequence of logical offsets
Language: Go - Size: 1.95 KB - Last synced at: about 2 months ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
DataSystemsGroupUT/Process-Discovery-over-unordered-streams
A Flink library to implement both a buffer-based and a speculative out-of-order event arrival handlers for online process discovery
Language: Java - Size: 43 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
RClabiisc/RV64IMAFDC---Superscalar-Single-core
Reconfigurable Computing Lab, DESE, Indian Institiute of Science
Size: 18.6 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
0mega28/CPU-Simulator
CENOS: The Modern CPU Simulator
Language: C++ - Size: 95.7 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
Amutheezan/Tomasulo 📦
Basic Implementation of Tomasulo Algorithm, with memory unit pipelined.
Language: Python - Size: 72.3 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
zhuangsc/RFC_marss86
Register file cache implementation on the Marssx86 architectural simulator
Language: C - Size: 14.2 MB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0
