GitHub / Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Awais-Asghar%2FSingle-Cycle-RISC-V-Processor-Implemented-on-FPGA
PURL: pkg:github/Awais-Asghar/Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

Topics: computer-architecture, cpu-architecture, digital-design-and-computer-organization, fpga, processor-design, risc-v, rv32i-processor, single-cycle-processor, system-verilog, vivado

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