Topic: "multi-cycle-cpu"
wzp21142/mips-cpu-and-microsystem
基于Verilog实现的三个MIPS架构CPU项目,按顺序实现了单周期,多周期以及基于多周期的微系统. Three Verilog-based MIPS CPU projects, simulate pipelined cpu based on mips instruction set:single-cycle, multi-cycle, and a microsystem based on the multi-cycle cpu.
Language: Verilog - Size: 273 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 9 - Forks: 1
Vedant2311/Complete-ARM-CPU
Single and Multi-cycle ARM processors implemented using VHDL
Language: VHDL - Size: 354 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
Moondok/cpu-54
A multi-cycle CPU which supports 54 Mips instructions
Language: Verilog - Size: 230 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
Santana-DS/OAC_GRUPO-B3
OAC - Grupo B3 - Lucas Santana e Gabriel Castro (CIC0099 - UnB 2025/1)
Language: VHDL - Size: 23.9 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
