Topic: "harvard-architecture-processor"
Passant-Abdelgalil/MIPS-Processor-Harvard-Architecture
A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.
Language: VHDL - Size: 23.7 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 6 - Forks: 1
Moondok/cpu-54
A multi-cycle CPU which supports 54 Mips instructions
Language: Verilog - Size: 230 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
kianmajl/A2K-CPU
A 32-bit single cycle RISC CPU based on Harvard architecture with no cache or pipeline, by having very simple and reduced instruction set it can be used for educational purpose.
Language: Verilog - Size: 294 KB - Last synced at: 27 days ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
mxligr/Custom-CPU
A VHDL design of a simple custom processor, designed as a project for the Structure of Computer Systems class // 3rd year, 1st semester @ TUCN
Language: VHDL - Size: 1.62 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
omarelhedaby/Harvard-Architecture-Processor
Implementation of Harvard Architecture Processor using VHDL
Language: VHDL - Size: 8.25 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
