Topic: "gate-level-simulation"
embedded-explorer/Open-Source-RTL-Design
This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
Language: Verilog - Size: 10.8 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 15 - Forks: 5
RohanNagar/parallel-logic-networks 📦
Gate-Level Simulation on a GPU
Language: C++ - Size: 2.26 MB - Last synced at: 11 months ago - Pushed at: over 8 years ago - Stars: 10 - Forks: 3
poshtkohi/pdes
A Parallel Discrete Event Simulation Engine with Examples
Language: C++ - Size: 6.96 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
alirezajaberirad/Object-Oriented-Modeling-of-Electronic-Circuits
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
Language: C++ - Size: 7.06 MB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0
Farbod-Siahkali/Digital-Logical-Designs-Projects
Digital Logical Designs Course Projects
Language: Verilog - Size: 4.66 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
VarshithGovi/Full-Adder-Design-Verilog
Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
Language: Verilog - Size: 11.7 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
VarshithGovi/2-to-1-Multiplexer-Design-Verilog
Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
Language: Verilog - Size: 17.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0
BhattSoham/RISCV-HDP
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
Language: Verilog - Size: 42.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
FarshidKeivanian/Optimization-of-JK-Flip-Flop-Layout-with-Minimal-Average-Power-of-Consumption-based-on-ACOR-Fuzzy-A
FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)
Language: MATLAB - Size: 1.06 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1
