digital-circuits | Topic | Ecosyste.ms: Repos

Topic: "digital-circuits"

logisim-evolution/logisim-evolution

Digital logic design tool and simulator

Language: Java - Size: 108 MB - Last synced at: 2 days ago - Pushed at: 6 days ago - Stars: 5,661 - Forks: 718

hneemann/Digital

A digital logic designer and circuit simulator.

Language: Java - Size: 37.8 MB - Last synced at: about 13 hours ago - Pushed at: about 1 month ago - Stars: 4,828 - Forks: 492

CircuitVerse/CircuitVerse

CircuitVerse Primary Code Base

Language: JavaScript - Size: 104 MB - Last synced at: 7 days ago - Pushed at: 14 days ago - Stars: 958 - Forks: 1,590

OpenCircuits/OpenCircuits

A free, open source, online digital circuit/logic designer.

Language: TypeScript - Size: 32.2 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 333 - Forks: 82

qdm12/hbc 📦

API of homomorphic binary operations such as binary comparisons or binary divisions using the library HElib

Language: C++ - Size: 3.56 MB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 29 - Forks: 5

ngdrascal/8bitsim

Simulation of Ben Eater's 8 bit computer running in the logic simulator called Digital

Size: 282 KB - Last synced at: 9 months ago - Pushed at: over 2 years ago - Stars: 16 - Forks: 3

abs-tudelft/tydi

Tydi: an open specification for complex data structures over hardware streams

Language: Rust - Size: 5.94 MB - Last synced at: 28 days ago - Pushed at: about 2 years ago - Stars: 15 - Forks: 6

JC-LL/ruby_rtl

Describing RTL circuit in Ruby

Language: Ruby - Size: 490 KB - Last synced at: 24 days ago - Pushed at: about 3 years ago - Stars: 10 - Forks: 0

mbezjak/vhdllab

Educational software for modelling and simulation of digital circuits.

Language: Java - Size: 45.3 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 10 - Forks: 6

lcbcFoo/circuitly

A visual and constructive framework for teaching digital circuits.

Language: JavaScript - Size: 237 KB - Last synced at: 9 months ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 0

georgejkaye/act2022-slides

Slides for my talk at ACT 2022, 'Fully abstract categorical semantics for digital circuits'

Language: TeX - Size: 95.7 KB - Last synced at: 14 days ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 0

xinoip/verilog-atpg

Generate ATPG for fault detection on Verilog circuits. C++/QT

Language: Verilog - Size: 3.5 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 0

MIPT-ILab/digital-design 📦

Lectures on Digital Design

Size: 24.8 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 2

Nozidoali/MapBuf

MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization

Language: Python - Size: 157 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 4 - Forks: 0

brickpool/Speedometer

Motorcycle LCD Digital Speedometer Odometer

Language: Ruby - Size: 2 MB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 1

michalusio/hoodoo_gpu_campaign

A custom campaign adding a GPU to the game Turing Complete

Size: 904 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 3 - Forks: 0

Thuffir/6502

Simple 6502 / 65C02 implementation

Language: C - Size: 386 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 2

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Language: Verilog - Size: 68.4 KB - Last synced at: 24 days ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0

georgejkaye/syco8-abstract

Extended abstract for my SYCO 8 talk, 'Normalisation by evaluation for digital circuits'

Language: TeX - Size: 24.4 KB - Last synced at: 14 days ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

JoshuaEbenezer/verilog-hdl

Smorgasbord of HDL codes

Language: Verilog - Size: 18.6 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 3 - Forks: 0

adityagupta1089/EEP206-Verilog

Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.

Language: Verilog - Size: 18.6 KB - Last synced at: over 1 year ago - Pushed at: almost 8 years ago - Stars: 3 - Forks: 2

edubr029/ufma

All source codes of the programs made during the Electrical Engineering course at UFMA

Language: C - Size: 152 KB - Last synced at: 22 days ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

Adr-hyng/74LS-Series-Fritzing-Parts

Fritzing parts for most common DIP ICs including 74LS Series and more, which is used in Digital Electronics or Logic Circuit and Design.

Size: 10.4 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

FireguiQueen/how-computers-really-work

My notes and explications from the book "How computers really work", by Matthew Justice.

Size: 315 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0

ZeroDashZero/32-bit-Multiplier-design-using-transistor-level-Digital-Gates

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

Size: 6.57 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 5

icarogabryel/flote

Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.

Language: Python - Size: 254 KB - Last synced at: 7 days ago - Pushed at: 8 days ago - Stars: 1 - Forks: 0

meghasv09/IntruderAlarmCircuit

A laser-based intruder alarm circuit that triggers the buzzer and LED when the laser beam is interrupted.

Size: 3.29 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

Viniciusog/ciencia-computacao-ufscar

Conteúdos, algoritmos e exercícios sobre diversas matérias do curso.

Language: Jupyter Notebook - Size: 486 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

georgejkaye/lfcs-seminar

Slides for my talk at the LFCS seminar, 'A compositional theory of digital circuits'

Language: TeX - Size: 1.39 MB - Last synced at: 14 days ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

Marwan-9/digital-logic-circuits-simulator

A Windows application for designing and simulating digital logic circuits, written in C++ using CMU graphics library.

Language: C - Size: 14.5 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

AdityaGirdhar/ascii-digital-display

A seven-segment-display decoding circuit based on a custom conversion scheme

Size: 3.78 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

arorashivoy/SemWiseNotesIIITD

Sem-wise note for the courses offered to CSAM branch in IIITD

Language: HTML - Size: 614 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

ajaycc17/digital-circuits

Digital Circuits demonstrated using MATLAB and LTSpice (IISER Bhopal)

Language: MATLAB - Size: 13.2 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

lucasmsoares96/Processador-16-bits

Processador monocíclo de 16 bits inspirado no livro Logic and Computer Design Fundamentals, de M. Morris Mano e Charles Kime.

Language: C - Size: 360 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

ronandrevon/electronics

Electronic related projects

Language: Python - Size: 8.1 MB - Last synced at: about 1 year ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

sgrmshrsm7/dcmplab

This repository contains my Digital Circuits and Micro Processor (DCMP) lab works.

Language: Assembly - Size: 85 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

ptrtonull-workshop/DigitalCircuitApi

电路数字化

Language: Java - Size: 58.6 KB - Last synced at: about 2 months ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

iBug/adc_lab 📦

Projects for course <Analog & Digital Circuits Lab>

Language: VHDL - Size: 2.43 MB - Last synced at: about 1 year ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 1

LFMP/CDII

Language: VHDL - Size: 58.9 MB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 1

abarichello/INE5406

INE5406 - Digital Systems

Language: VHDL - Size: 260 KB - Last synced at: 2 months ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

rafagarcia2/simulador_circuitos_digitais

Simulador de Circuitos Digitais - Projeto de Polimorfismo

Language: C++ - Size: 620 KB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

levindoneto/Digital_Circuits

Digital Circuits made for some exercises of the Digital Circuits Course of the Brazilian platform Me Salva!. The circuits have been implemented on Logisim.

Size: 19.5 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

pgombar/aes-project

Optimizing AES key generation routine in VHDL.

Language: VHDL - Size: 1.09 MB - Last synced at: about 1 year ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 2

K4V4NH/Basic-Verilog-Codes

Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.

Language: Verilog - Size: 18.6 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

Nyfeu/BIP-I

This VHDL code describes the architecture of a simplified Central Processing Unit (CPU). The CPU is capable of executing basic instructions stored in ROM, using an accumulator (ACC) and an Arithmetic Logic Unit (ALU) for arithmetic and logical operations. It uses a Harvard bus architecture.

Language: VHDL - Size: 388 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

AskarAbdullaev/pylogex

Python utilities for studying logic including Finite Automata, Oracles, Kripke Structures, Process Algebra, LTL, CTL, Petri Nets, Propositional Logic, BCP, DPLL, Resolution, Blocked Clauses, Equational Reasoning, Term Matching, Term Reduction, Critical Pairs, Knuth-Bendix Completion, etc.

Language: Jupyter Notebook - Size: 1.51 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

blubberdiblub/tc_campaign Fork of Stuffe/tc_campaign

Campaign levels of the game `Turing Complete`

Size: 639 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

CFZRfrndVolt/Introducing-VHDL-

This repository contains projects and experiments focused on designing, simulating, and implementing digital circuits using VHDL (VHSIC Hardware Description Language) and Quartus II software. The projects covered in this repository serve as an introduction to key concepts in digital system design, including the creation of basic logic circuits, com

Size: 1000 Bytes - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

jakunzler/asic_fpga_introduction

Web page for the ASIC and FPGA Repository

Language: Dockerfile - Size: 63.9 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

fermarsan/Multiplier_4b_sim

This example implements a digital 4-bit sequential multiplier simulation on SimulIDE

Language: AngelScript - Size: 370 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

HarinandanAM/FPGA

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. Each project includes HDL code, testbenches, simulations, and pin assignments, providing a comprehensive view of the FPGA design process.

Language: VHDL - Size: 82 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Arsham-LH/Logic-Circuits

Simulation of logic circuits using Verilog, Proteus and other tools.

Language: Verilog - Size: 2.88 MB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

eduardoBorgonha/mastermind-ctd

Esse é o projeto final da disciplina de Circuitos e Técnicas Digitais, ofertada pelo departamento de Engenharia Elétrica da UFSC. Ele consiste em programar uma FPGA para rodar o jogo mastermind.

Language: VHDL - Size: 9.77 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Davide-Ettori/Memory_Interaction-Hardware-Component-FPGA

Digital Circuits Design Project (PoliMi, year 2022) - Memory Interaction

Language: VHDL - Size: 7.3 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Mightlaus/CLA-full-adder

A high-performance and versatile carry-lookahead (CLA) full adder designed for rapid addition of arbitrary x^y bit inputs.

Language: Verilog - Size: 18.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

xixihahahha/digitalcircuit

数字电路实验

Language: Verilog - Size: 3.54 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

guiogigo/GuessTheNumberXTREME

O projeto trata-se de um jogo de adivinhação contruído inteiramente no Logisim como método de avaliação para a cadeira de Circuitos Digitais 2023.1 da UFCA

Size: 187 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0