Topic: "axi"
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Language: SystemVerilog - Size: 9.12 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 1,279 - Forks: 290
taichi-ishitani/tvip-axi
AMBA AXI VIP
Language: SystemVerilog - Size: 153 KB - Last synced at: 4 days ago - Pushed at: 11 months ago - Stars: 401 - Forks: 112
rggen/rggen
Code generation tool for control and status registers
Language: Ruby - Size: 510 KB - Last synced at: 21 days ago - Pushed at: 3 months ago - Stars: 381 - Forks: 46
ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Language: Verilog - Size: 15.1 MB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 273 - Forks: 43
taichi-ishitani/tnoc
Network on Chip Implementation written in SytemVerilog
Language: SystemVerilog - Size: 406 KB - Last synced at: 2 months ago - Pushed at: almost 3 years ago - Stars: 171 - Forks: 46
hdl-modules/hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Language: VHDL - Size: 3.63 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 165 - Forks: 29
SystemRDL/PeakRDL
Control and status register code generator toolchain
Language: Python - Size: 136 KB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 134 - Forks: 28
hdl-registers/hdl-registers
An open-source HDL register code generator fast enough to run in real time.
Language: Python - Size: 2.19 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 64 - Forks: 8
lucky-wfw/ARM_AMBA_Design
Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
Language: Verilog - Size: 2.93 MB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 61 - Forks: 26
RSPwFPGAs/opae-xilinx
OPAE porting to Xilinx FPGA devices.
Language: Coq - Size: 6.66 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 33 - Forks: 13
d953i/Custom_Part_Data_Files
Xilinx PCIe to MIG DDR4 example designs and custom part data files
Language: Tcl - Size: 28.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 28 - Forks: 17
wyvernSemi/mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
Language: VHDL - Size: 2.71 MB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 22 - Forks: 3
Wissance/QuickSPI
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Language: Verilog - Size: 127 KB - Last synced at: about 2 months ago - Pushed at: over 7 years ago - Stars: 22 - Forks: 7
pulp-platform/axi_mem_if
Simple single-port AXI memory interface
Language: SystemVerilog - Size: 62.5 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 19 - Forks: 19
pulp-platform/axi_node 📦
AXI X-Bar
Language: SystemVerilog - Size: 187 KB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 19 - Forks: 35
hplp/aes_chisel
Implementation of the Advanced Encryption Standard in Chisel
Language: Scala - Size: 579 KB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 18 - Forks: 2
esynr3z/axi_vip_demo
Xilinx AXI VIP example of use
Language: SystemVerilog - Size: 4.83 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 13 - Forks: 6
rggen/rggen-sv-rtl
Common SystemVerilog RTL modules for RgGen
Language: SystemVerilog - Size: 117 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 12 - Forks: 2
mwrnd/innova2_xcku15p_ddr4_bram_gpio
XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
Language: Tcl - Size: 6.91 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 12 - Forks: 2
Yourigh/Rotary-encoder-VHDL-design
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
Language: VHDL - Size: 25.4 KB - Last synced at: almost 2 years ago - Pushed at: about 8 years ago - Stars: 10 - Forks: 2
olagrottvik/bust
Utility for creating and modifying VHDL bus slave modules
Language: Python - Size: 7.85 MB - Last synced at: 14 days ago - Pushed at: 3 months ago - Stars: 9 - Forks: 1
RISMicroDevices/OpenNCB 📦
Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)
Language: Scala - Size: 329 KB - Last synced at: 23 days ago - Pushed at: 8 months ago - Stars: 9 - Forks: 1
pothosware/PothosFPGA
Pothos FPGA computational offload and buffer integration support
Language: VHDL - Size: 26.9 MB - Last synced at: 3 months ago - Pushed at: almost 10 years ago - Stars: 9 - Forks: 1
abdelazeem201/Arm-Core
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
Language: C - Size: 6.94 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 8 - Forks: 1
MicroTCA-Tech-Lab/libudmaio
Userspace I/O library for Xilinx AXI S2MM DMA
Language: C++ - Size: 43.6 MB - Last synced at: 5 days ago - Pushed at: 3 months ago - Stars: 7 - Forks: 2
plasoc/axiplasma
AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.
Language: VHDL - Size: 135 MB - Last synced at: about 1 year ago - Pushed at: about 7 years ago - Stars: 7 - Forks: 1
vedranMv/axi_spi_master
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
Language: VHDL - Size: 27.3 KB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 7 - Forks: 0
kuoyaoming93/sem-ip_pynq
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
Language: Tcl - Size: 17.8 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 5 - Forks: 1
gednyengs/dma
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
Language: Scala - Size: 4.46 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 3
pulp-platform/axi2per
AXI to Peripheral Interconnect
Language: SystemVerilog - Size: 36.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 1
MatthieuMichon/fpga-jtag-axi-demo
Basic JTAG / AXI demonstration on Xilinx's FPGA.
Language: Tcl - Size: 19.5 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 1
pedrovt/cr-labs
Labs of the Reconfigurable Computing course, University of Aveiro
Language: VHDL - Size: 108 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 1
aryan-programmer/axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Language: TeX - Size: 191 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
pkill37/asic-linreg
ASIC for executing vectorized gradient descent on linear regression problems.
Language: VHDL - Size: 110 MB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 1
hdlguy/axi_sim
just some files that show one simple way to simulate some axi cycles.
Language: Verilog - Size: 23.4 KB - Last synced at: about 2 years ago - Pushed at: about 9 years ago - Stars: 2 - Forks: 0
SACHINUR17/VLSI-Design-Verification-Projects
This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects
Language: Verilog - Size: 134 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1 - Forks: 0
Ajao-Victor/Fol
Fol app is a hands-on full-stack learning app built with React, Node, Express & PostgreSQL. Sign up to explore real-time examples, live code demos, and practical tutorials—all freely accessible and deployed on GitHub to help you learn by doing. Perfect for beginners and curious devs!
Language: JavaScript - Size: 18.8 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0
yasnakateb/VectorOps
🏄 Custom IP for vector operations
Language: VHDL - Size: 540 KB - Last synced at: 3 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0
opifexM/RSS-Aggregator
RSS Aggregator is a web application that collects, parses, and displays news feeds from various sources, offering a multi-language, user-friendly interface for managing and reading RSS feeds.
Language: JavaScript - Size: 983 KB - Last synced at: 3 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0
AranelLindi/AXI_SpaceWire_IP
Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).
Language: VHDL - Size: 59.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
igor-sergeevich-po/affordable-housing
Сервис по подбору доступного жилья.
Language: JavaScript - Size: 9.26 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
Kampi/OV7670
FPGA interface and driver for an OV7670 camera sensor.
Language: VHDL - Size: 31.3 KB - Last synced at: about 1 hour ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 1
mrengineer/Zynq7000_simpleDMA_IRQ_vivado_linux_userspace
Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.
Language: VHDL - Size: 81.6 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
vacagonzalo/soc-workflow-vhdl
Example workflow project for VHDL development.
Language: VHDL - Size: 12.7 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
Simonpedro/axie-team-builder
Set of useful tools around the Axie infinity game.
Language: TypeScript - Size: 90.8 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
iDoka/statistics-acquisition-module
Statistics Acquisition Module on Verilog
Size: 0 Bytes - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0
narendiran1996/AXILearning
Learning Resources for AXI made by self
Language: VHDL - Size: 6.92 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0
Bucknalla/axis-interfacer
Extract AXI (Full, Lite and Stream) interfaces from Verilog source files
Size: 37.1 KB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
gururavi/rtl
Synchronous and Asynchronous FIFO with AXI interface
Language: SystemVerilog - Size: 9.77 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0
cong2738/May_team_project_I2C_SPI
i2c com, spi com with AMBA AXI
Language: VHDL - Size: 71.5 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 3
atfox272/DVP-RX-Controller
This repository contains the RTL code of a DVP (Digital Video Port) TX Controller with AXI4 interface in the application layer.
Language: Verilog - Size: 779 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 0 - Forks: 0
atfox272/dma
RTL code for DMA controller
Language: SystemVerilog - Size: 802 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 0 - Forks: 0
RadioactiveScandium/Digital-Interfaces
Knowledge hub for digital interfaces
Language: SystemVerilog - Size: 3.17 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
Fcatilizer/Web-Video-Streaming
A Web Video Streaming Application
Language: JavaScript - Size: 19.8 MB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
ubyhzargam/AMBA-Protocol-Family
This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm
Language: Verilog - Size: 4.88 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
SkyVerify/AXI4_VIP
AXI4 Verification IP
Language: SystemVerilog - Size: 1.48 MB - Last synced at: 7 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0
rodrigomelo9/amba
A presentation about Advanced Microcontroller Bus Architecture
Language: SystemVerilog - Size: 3.51 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
ipapal/axi-dma-petalinux
AXI DMA with Petalinux
Size: 8.79 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
IlyaChichkov/AXI_Counter
Реализация AXI интерфейса на SystemVerilog
Language: SystemVerilog - Size: 61.5 KB - Last synced at: about 23 hours ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
Florin623/AXI-Lite-Slave-FFT-IP
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
Language: VHDL - Size: 71.2 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Florin623/AXI-Lite-Slave-FPU-IP
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
Language: VHDL - Size: 142 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Mohamed-Ramadan1/Mix-Master
Language: JavaScript - Size: 93.8 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
suoglu/AXI-GPIO
Custom AXI GPIO core with up to 32 input and 32 output ports
Language: Tcl - Size: 39.1 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
Takeru9016/airbnb-clone
Language: TypeScript - Size: 629 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
imhcyx/axi.vh
Verilog header for easier AXI interface declaration & connection
Language: SystemVerilog - Size: 5.86 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
PoliTo-ASAC-Lab/PYNQ_UARTopus
Python platform to use a TUL PYNQ-Z2 development board to virtualize up to 12 UART connections (tx+rx@9600bps) over TCP-IP
Language: Python - Size: 44.4 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
mjh-design/verilog-axis Fork of alexforencich/verilog-axis
Verilog AXI stream components for FPGA implementation
Size: 1.08 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
mjh-design/AXI_DMA Fork of wanderingnail/AXI_DMA
一个基于AXI的DMA
Size: 2.59 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
anmol109/AMBA-AXI4-Lite
An implementation of AMBA AXI4Lite on an FPGA using verilog
Language: Verilog - Size: 26.8 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
mjh-design/AXI_spec_chinese Fork of lizhirui/AXI_spec_chinese
AXI协议规范中文翻译版
Size: 478 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
Onlynfk/my-spotify-reactjs
Spotify Clone With Reactjs
Language: JavaScript - Size: 619 KB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
deian-mishev/click_bait_filter_be
Click Bait Filter Backend (Prototype_Server)
Language: JavaScript - Size: 511 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
kuoyaoming93/axi_uartlite_pynq Fork of parthpower/axi_uartlite_pynq
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
Language: Tcl - Size: 15.9 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0
mjh-design/DMA-S2MM-and-MM2S Fork of 2cc2ic/DMA-S2MM-and-MM2S
Build an open source, extremely simple DMA.
Size: 165 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0