Topic: "sdram"
ultraembedded/cores
Various HDL (Verilog) IP Cores
Language: Verilog - Size: 211 KB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 745 - Forks: 218
nullobject/sdram-fpga
A FPGA core for a simple SDRAM controller.
Language: VHDL - Size: 119 KB - Last synced at: 11 days ago - Pushed at: over 3 years ago - Stars: 118 - Forks: 27
hdl-util/sdram-controller
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
Language: Verilog - Size: 1.54 MB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 79 - Forks: 11
1a2m3/SPD-Reader-Writer
SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus
Language: C# - Size: 50.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 70 - Forks: 13
jasonsbeer/Amiga-N2630
A re-imagining of the Amiga A2630 processor card.
Language: KiCad Layout - Size: 1.32 GB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 43 - Forks: 7
ghent360/riscvOnColorlight-5A-75B Fork of trabucayre/litexOnColorlightLab004
RISC-V soft core running on Colorlight 5B-74B.
Language: C - Size: 56.6 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 28 - Forks: 6
iliasam/stm32f429_vga_examples
Code examples of using STM32F429 for generating VGA image.
Language: C - Size: 6.01 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 24 - Forks: 8
machdyne/kuchen
Kuchen Computer
Language: OpenSCAD - Size: 1.3 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 22 - Forks: 2
oscc-ip/sdram
An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
Language: Scala - Size: 2.11 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 17 - Forks: 2
qubeck78/tangerineA7_200
RiscV based SOC for Qmtech Artix A7-200 board. Includes nekoRv: RISC-V 32 IM Zicsr core. And yes, it runs DOOM :)
Language: VHDL - Size: 1.27 GB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 17 - Forks: 0
perehinik/SDRAM_Controller
Verilog SDR SDRAM controller for FPGA Xilinx and Lattice
Language: VHDL - Size: 4.25 MB - Last synced at: 5 days ago - Pushed at: over 4 years ago - Stars: 16 - Forks: 4
splinedrive/my_sdram
simple sdram controller
Language: Verilog - Size: 5.81 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 14 - Forks: 3
AngeloJacobo/FPGA_SDRAM_Controller
SDRAM controller optimized to a memory bandwidth of 316MB/s
Language: Verilog - Size: 18.6 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 13 - Forks: 1
har-in-air/SIPEED_TANG_PRIMER
Projects using the Sipeed Tang Primer FPGA development board
Language: Verilog - Size: 1.7 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 11 - Forks: 0
cw1997/SDRAM-Controller
SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
Language: HTML - Size: 1.5 MB - Last synced at: 2 months ago - Pushed at: almost 3 years ago - Stars: 10 - Forks: 2
andrempmattos/harsh-payload
Harsh Environment CubeSat Payload designed to evaluate three different manufacturing nodes SDR SDRAM technologies under space radiation conditions. It was developed for the FloripaSat-2 CubeSat mission.
Language: VHDL - Size: 218 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 9 - Forks: 2
MinatsuT/CYC1000_SDRAM
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
Language: Verilog - Size: 554 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 9 - Forks: 0
Arkowski24/sdram-controller
Simple SDRAM Controller for DE10-Lite.
Language: Verilog - Size: 71.3 KB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 9 - Forks: 3
briansune/max-II-cpld-sdram-tft-driver
Language: C - Size: 13.3 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 0
egk696/EDAC_SDRAM_Controller
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
Language: Verilog - Size: 94.4 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 8 - Forks: 2
jakubcabal/sdram-tester-fpga
SDRAM Tester implemented in FPGA
Language: VHDL - Size: 60.5 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 7 - Forks: 1
redchenjs/spd-eeprom
A simple command line tool for reading and writing AT24/EE1004 SPD EEPROMs.
Language: Python - Size: 18.6 KB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0
vitalych/fpga-gameoflife
A game-of-life implementation for the FPGA4U board, with SDRAM, RS232 UART, and VGA controllers
Language: VHDL - Size: 7.16 MB - Last synced at: 9 days ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 0
agg23/sdram-controller
A HDL SDRAM controller designed for retro hardware and FPGAs
Language: SystemVerilog - Size: 61.5 KB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 3
briansune/Spartan_3_sdram_ftf_driver
Language: Verilog - Size: 15.4 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 1
abelykh0/stm32f746-sdram
Using SDRAM on a WaveShare STM32F746IGT6 board
Language: C - Size: 713 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 1
yigitbektasgursoy/SDRAM_Verilog
Verilog HDL implementation of SDRAM controller and SDRAM model
Language: Verilog - Size: 781 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0
fredrequin/verilator_helpers
C++ objects to help verilator simulations
Language: C - Size: 149 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0
armleo/sdram_controller
SDR SDRAM Controller with Avalon-MM bus;
Language: Verilog - Size: 1.36 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 1
RichardPar/SDRAM_Controller_Verilog
This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz.
Language: Verilog - Size: 554 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1
Emilylulu/Implementation-of-SDRAM-interface-with-a-parallel-bus-in-Verilog
Language: Verilog - Size: 13.7 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 0
teekamkhandelwal/SRAM_Controller
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
Language: Verilog - Size: 72.3 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0
oskarwires/sdram_controller
High-Speed SystemVerilog SDRAM Controller
Language: SystemVerilog - Size: 151 KB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
SoCXin/SWM34S
L2 R4: Synwit 150MHz Cortex-M33 LCD MCU (SWM34S)
Language: C - Size: 52.4 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1
kitune-san/KFSDRAM
Simple SDRAM controller written in SystemVerilog
Language: SystemVerilog - Size: 199 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0
yasnakateb/SdramController
🛠 A SDRAM controller in Verilog HDL
Language: Verilog - Size: 47.9 KB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0
Keidan/STM32F7_MEMORY_MAPPED_SDRAM
(LGPL) Demonstration of how to use a memory-mapped SDRAM through the Flexible Memory Controller
Language: C - Size: 768 KB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 1 - Forks: 1
jairov4/puj-ca-de1-audio-pump
Base files for project in Computer Architecture course of 2014-2
Language: C - Size: 1.68 MB - Last synced at: about 1 year ago - Pushed at: about 10 years ago - Stars: 1 - Forks: 0
Edwyrion/sdram-controller
Basic implementation of SDRAM controller for De0-nano board.
Language: Verilog - Size: 15.6 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0
gravitamp/SDRAM-H743
Language: C - Size: 7.5 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
zoosmand/STM32F429I-disk1__LL_HAL_periph__template
An initial project for STM32F429ZI (aka STM32F429I-Disco1). It uses LL but no HAL.
Language: C - Size: 7.11 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
