GitHub / hdl-util / sdram-controller
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fsdram-controller
Stars: 79
Forks: 11
Open issues: 0
License: other
Language: Verilog
Size: 1.54 MB
Dependencies parsed at: Pending
Created at: about 5 years ago
Updated at: 7 months ago
Pushed at: almost 5 years ago
Last synced at: 3 months ago
Topics: as4c4m16sa, controller, dram, fpga, quartus, sdram, systemverilog
Funding Links https://github.com/sponsors/sameer
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