Ecosyste.ms: Repos
An open API service providing repository metadata for many open source software ecosystems.
GitHub topics: dram
liquidctl/liquidctl
Cross-platform CLI and Python drivers for AIO liquid coolers and other devices
Language: Python - Size: 4.03 MB - Last synced: about 13 hours ago - Pushed: 17 days ago - Stars: 2,121 - Forks: 209
ThexXTURBOXx/Raspberry-Pi-DRAM-PUF
Decay-based DRAM PUF for the Raspberry Pi 3B+ implemented on top of rpi-open-firmware
Language: C - Size: 59.1 MB - Last synced: 7 days ago - Pushed: 7 days ago - Stars: 1 - Forks: 1
CMU-SAFARI/ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Language: C++ - Size: 659 KB - Last synced: 13 days ago - Pushed: 13 days ago - Stars: 165 - Forks: 42
hdl-util/sdram-controller
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
Language: Verilog - Size: 1.54 MB - Last synced: 23 days ago - Pushed: almost 4 years ago - Stars: 76 - Forks: 10
CMU-SAFARI/DRAM-Bender
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
Language: VHDL - Size: 70.7 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 38 - Forks: 6
CMU-SAFARI/CLRDRAM
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf
Language: AGS Script - Size: 20.5 KB - Last synced: about 2 months ago - Pushed: over 3 years ago - Stars: 9 - Forks: 7
CMU-SAFARI/BEER
BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.
Language: C++ - Size: 7.5 MB - Last synced: about 2 months ago - Pushed: over 3 years ago - Stars: 17 - Forks: 0
PlatformLab/RAMCloud
**No Longer Maintained** Official RAMCloud repo
Language: C++ - Size: 13.3 MB - Last synced: about 2 months ago - Pushed: over 4 years ago - Stars: 481 - Forks: 141
umd-memsys/DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
Language: C++ - Size: 8.05 MB - Last synced: 4 months ago - Pushed: over 3 years ago - Stars: 234 - Forks: 149
adarshpatil/dve
Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]
Language: Objective-C - Size: 174 KB - Last synced: about 2 months ago - Pushed: about 2 years ago - Stars: 7 - Forks: 1
tukl-msd/DRAMSpec
A High-Level DRAM Timing, Power and Area Exploration Tool
Language: C++ - Size: 400 KB - Last synced: 3 months ago - Pushed: almost 4 years ago - Stars: 16 - Forks: 11
CMU-SAFARI/EINSim
DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.
Language: C++ - Size: 19 MB - Last synced: about 2 months ago - Pushed: 6 months ago - Stars: 9 - Forks: 2
cdslaborg/paramontex
This is a repository for the ParaMonte library examples. For more information, visit:
Language: Jupyter Notebook - Size: 210 MB - Last synced: 4 months ago - Pushed: over 2 years ago - Stars: 4 - Forks: 7
mjlaine/mcmcstat
MCMC toolbox for Matlab
Language: MATLAB - Size: 2.32 MB - Last synced: 8 months ago - Pushed: almost 3 years ago - Stars: 68 - Forks: 29
dovedevic/blimp
A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.
Language: C - Size: 81.1 KB - Last synced: 6 months ago - Pushed: about 2 years ago - Stars: 14 - Forks: 4
adarshpatil/gem5gpu-hashcache
HAShCache + Intergrated CPU/GPU system simulation setup
Language: C++ - Size: 13.1 MB - Last synced: 10 months ago - Pushed: almost 2 years ago - Stars: 1 - Forks: 1
guptaaniket261/DRAM-Request-Manager-Multicore-Processor
DRAM Request Manager for Multicore Processors
Language: C++ - Size: 1.86 MB - Last synced: 10 months ago - Pushed: about 3 years ago - Stars: 0 - Forks: 1
CMU-SAFARI/HARP
HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/2109.12697.
Language: C++ - Size: 2.59 MB - Last synced: about 2 months ago - Pushed: over 2 years ago - Stars: 7 - Forks: 1
JakubKajzer/Trugbild
An FPGA working in serial with HDMI, for some real live video modifications
Size: 9.84 MB - Last synced: 11 months ago - Pushed: almost 3 years ago - Stars: 0 - Forks: 0
CMU-SAFARI/DRAM-Voltage-Study
Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs
Language: AGS Script - Size: 242 KB - Last synced: about 2 months ago - Pushed: almost 7 years ago - Stars: 5 - Forks: 8
wgurecky/bipymc
Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.
Language: Python - Size: 1.87 MB - Last synced: 7 months ago - Pushed: almost 4 years ago - Stars: 6 - Forks: 3
enascimento/rowhammer-test Fork of google/rowhammer-test
Test DRAM for bit flips caused by the rowhammer problem
Size: 408 KB - Last synced: about 1 year ago - Pushed: almost 9 years ago - Stars: 0 - Forks: 1
CMU-SAFARI/DRAM-Datasheet-Survey
A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
Size: 10.7 KB - Last synced: about 2 months ago - Pushed: about 2 years ago - Stars: 6 - Forks: 1
pjattke/awesome-rowhammer
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
Size: 13.7 KB - Last synced: 23 days ago - Pushed: almost 2 years ago - Stars: 4 - Forks: 0
lmartorella/dram-tester
Tester for DRAM modules
Language: Makefile - Size: 1.06 MB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 1 - Forks: 0
comsec-group/REM
REGA Model (REM), an accurate DRAM model.
Language: AGS Script - Size: 96.7 KB - Last synced: over 1 year ago - Pushed: over 1 year ago - Stars: 3 - Forks: 0
NamhoGim/Master_thesis 📦
Repo for my master thesis
Language: TeX - Size: 14.4 MB - Last synced: 6 months ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 0
johnzl-777/DRAMutils
A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips
Language: C++ - Size: 2.8 MB - Last synced: over 1 year ago - Pushed: over 5 years ago - Stars: 4 - Forks: 0
blark/a500plus-chipram-expansion
A 1MB chip RAM expansion for the A500+
Size: 8.22 MB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 22 - Forks: 1
olemon111/SWP-Tree-BG2
Background Test for SWP-Tree
Language: C++ - Size: 847 KB - Last synced: 11 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0
Stephen-Arsenault/DRAM-Liberator Fork of ksercan5/DRAM_Tester_Arduino
DRAM Tester Shield for Arduino Nano
Language: C++ - Size: 2.23 MB - Last synced: over 1 year ago - Pushed: about 2 years ago - Stars: 3 - Forks: 0
llopis/dram-tester
Sample Arduino program to test 4164 DRAM chips.
Language: C++ - Size: 1.95 KB - Last synced: over 1 year ago - Pushed: about 3 years ago - Stars: 15 - Forks: 3
CMU-SAFARI/DIVA-DRAM
This repository provides characterization data collected over 96 DDR3 SO-DIMMs, related to the following paper: Lee et al., "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms", SIGMETRICS 2017. https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-paper.pdf
Language: AGS Script - Size: 510 MB - Last synced: about 2 months ago - Pushed: over 6 years ago - Stars: 5 - Forks: 3
mohin7/dramkit1
Demo: https://mohin7.github.io/dramkit1/
Language: HTML - Size: 2.22 MB - Last synced: over 1 year ago - Pushed: about 5 years ago - Stars: 1 - Forks: 0
gaomy3832/energydram
DRAM energy calculation.
Language: Python - Size: 46.9 KB - Last synced: 11 days ago - Pushed: almost 2 years ago - Stars: 1 - Forks: 0
saiteja-talluri/Microarchitectural-attacks
Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.
Language: C - Size: 10 MB - Last synced: over 1 year ago - Pushed: almost 5 years ago - Stars: 8 - Forks: 3
GauravJain28/CPU-and-DRAM-Simulator
Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi
Language: C++ - Size: 14.6 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 0
aayushgoyal443/Multicore-MIPS-ISA-Simulator
A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.
Language: C++ - Size: 2.76 MB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 0 - Forks: 0
5ayam5/COL216-A5
A multi-core MIPS simulator with Memory Request Manager for reordering DRAM requests to maximise throughput
Language: C++ - Size: 418 KB - Last synced: over 1 year ago - Pushed: about 3 years ago - Stars: 0 - Forks: 0
5ayam5/COL216-A4
MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution
Language: C++ - Size: 252 KB - Last synced: over 1 year ago - Pushed: about 3 years ago - Stars: 0 - Forks: 2
5ayam5/COL216-Minor
MIPS ISA simulator which implements non-blocking DRAM access
Language: C++ - Size: 427 KB - Last synced: over 1 year ago - Pushed: about 3 years ago - Stars: 0 - Forks: 0