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Topic: "verilog-processor"

krutideepanpanda/RISC-V-based-micro-controller-using-OpenLane

This is part of EC383 - Mini Project in VLSI Design.

Language: Verilog - Size: 16.6 MB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 0

sudhamshu091/RISC-Pipelined-Processor-32-bit-Verilog

Simple Pipelined 32 bit RISC Processor

Language: Verilog - Size: 195 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 7 - Forks: 1

SKpro-glitch/Resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

Size: 270 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 0 - Forks: 0

naftali10/Single-Cycle-MIPS

A System Verilog processor design of a single cycle MIPS architecture

Language: SystemVerilog - Size: 54.7 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

Related Topics
verilog 3 verilog-project 2 drone 1 electronics-engineering 1 java 1 java-programming 1 ltspice 1 matlab 1 soham-kapur 1 sohamkapur 1 team-aviators-international 1 uav 1 verilog-hdl 1 vit-chennai 1 vit-university 1 vitc 1 vitchennai 1 cadence-virtuoso 1 cadence 1 algorithms-and-data-structures 1 risc-v 1 risc 1 pipeline-risc 1 vlsi-design 1 vlsi 1 openlane-flow 1 openlane 1 mips-architecture 1 mips 1 microarchitecture 1 architecture 1