GitHub / muhammadtalhasami / verilog_practice
Verilog is a hardware description language. This repo is basically a learning journey of verilog
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Stars: 1
Forks: 0
Open issues: 0
License: None
Language: Verilog
Size: 5.86 KB
Dependencies parsed at: Pending
Created at: over 1 year ago
Updated at: 11 months ago
Pushed at: over 1 year ago
Last synced at: 2 months ago
Topics: design, gtkwave, hardware-designs, testbench, verilog-, vhdl
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