Topic: "ip-core"
jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Language: VHDL - Size: 1.42 MB - Last synced at: 14 days ago - Pushed at: over 6 years ago - Stars: 452 - Forks: 64
WangXuan95/FPGA-MPEG2-encoder
FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器，可实现视频压缩。
Language: Verilog - Size: 22.2 MB - Last synced at: 10 months ago - Pushed at: about 1 year ago - Stars: 97 - Forks: 17
Parretto/DisplayPort
DisplayPort IP-core
Language: SystemVerilog - Size: 6.12 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 62 - Forks: 11
iDoka/GOST-28147-89
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
Language: Verilog - Size: 34.2 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 12 - Forks: 2
rohitk-singh/usb-device
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
Language: Verilog - Size: 35.2 KB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 9 - Forks: 3
Paebbels/pyIPCMI
A Python-based IP Core Management Infrastructure.
Language: Python - Size: 578 KB - Last synced at: 5 days ago - Pushed at: almost 4 years ago - Stars: 8 - Forks: 6
esynr3z/pip-hdl
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
Language: Python - Size: 55.7 KB - Last synced at: 6 days ago - Pushed at: about 1 year ago - Stars: 7 - Forks: 0
vedranMv/axi_spi_master
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
Language: VHDL - Size: 27.3 KB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 7 - Forks: 0
Goshik92/FpgaCha
Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)
Language: C++ - Size: 85 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 1
iDoka/GOST-R34.12-2015
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
Language: Verilog - Size: 13.7 KB - Last synced at: about 2 years ago - Pushed at: about 8 years ago - Stars: 6 - Forks: 2
iDoka/ipyxact Fork of olofk/ipyxact
Python-based IP-XACT parser
Language: Python - Size: 50.8 KB - Last synced at: about 2 years ago - Pushed at: about 8 years ago - Stars: 5 - Forks: 1
iDoka/ipxact-cli-tools Fork of tudortimi/rgen
IP-XACT based CLI-tools
Language: Mako - Size: 30.3 KB - Last synced at: about 2 years ago - Pushed at: about 8 years ago - Stars: 4 - Forks: 2
rubinsteina13/SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
Language: SystemVerilog - Size: 83 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 2
Teddy-van-Jerry/ip-doc
LaTeX Class for IP Core Documentation
Language: TeX - Size: 803 KB - Last synced at: 19 days ago - Pushed at: 6 months ago - Stars: 2 - Forks: 0
rubinsteina13/SV_CLARKE_TRANSFORMATION_CORES
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
Language: SystemVerilog - Size: 24.4 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0
rubinsteina13/SV_DSM_CORE
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
Language: SystemVerilog - Size: 50.8 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 1
magictaler/RGB-LED-PWM-Demo-for-Arty-Z7-20
RGB PWM LED Demo project running on ARTY Z7-20 hardware
Language: C - Size: 110 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0
sbaldzenka/uart_core
UART IP-core for FPGA.
Language: VHDL - Size: 26.4 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0
sigma-logic/common-cores
Common cores for internal use under organization. Mostly oriented on Gowin Arora V family
Language: SystemVerilog - Size: 92.8 KB - Last synced at: 16 days ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
gonzafernan/cese-mys-zynq7
Microarquitecturas y Softcores - CESE - FIUBA
Language: Verilog - Size: 1.25 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
FlorianFrank/Verilog-UART-Custom-IP
A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.
Language: Verilog - Size: 94.7 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
jnonino-crpisetta-icomp/informe
Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
Language: TeX - Size: 14 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 1
