GitHub / jgelfman / Dataflow-Based-FPGA-Program-Synthesis-Capstone
An FPGA Program Generator written in Python that takes dsp-sig XML Dataflow Graphs created using FAUST to produce FPGA programs in VHDL.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jgelfman%2FDataflow-Based-FPGA-Program-Synthesis-Capstone
PURL: pkg:github/jgelfman/Dataflow-Based-FPGA-Program-Synthesis-Capstone
Stars: 3
Forks: 0
Open issues: 0
License: None
Language: VHDL
Size: 3.46 MB
Dependencies parsed at: Pending
Created at: over 4 years ago
Updated at: about 1 year ago
Pushed at: about 4 years ago
Last synced at: about 1 year ago
Topics: dataflow-compiler, dataflow-programming, dsp, fpga, fpga-programming, vhdl, vivado