nelsoncsc/ISP_UVM

A Framework for Design and Verification of Image Processing Applications using UVM

Language: SystemVerilog - Size: 499 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 64 - Forks: 27

nelsoncsc/easyUVM

A simple UVM example with DPI

Language: SystemVerilog - Size: 7.81 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 28 - Forks: 12

JoseIuri/Simple_UVM

Implements a simple UVM based testbench for a simple memory DUT.

Language: SystemVerilog - Size: 56.6 KB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 10 - Forks: 5

rooinasuit/AXI_to_SPI

Designing means to communicate as an SPI master, being a part of AXI interface

Language: Verilog - Size: 12.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 2

nelsoncsc/basic_uvmc_oct

A simple UVM testbench using UVM Connect and Octave

Language: SystemVerilog - Size: 7.81 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 7 - Forks: 0

MarleyLobao/UVM_calculator

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

Language: SystemVerilog - Size: 135 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0

fvutils/pyuvm-dataclasses

Apply dataclasses concept to testbench automation in Python

Language: Python - Size: 236 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

nelsoncsc/basic_uvmc

A simple testbench with two refmods using UVM Connect

Language: SystemVerilog - Size: 9.77 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 2

zuspec/zuspec-parser

Language parser

Language: C++ - Size: 4.69 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 1 - Forks: 0

OmniaMohamed12/AES-128-Verification-Using-UVM

Verification of Advanced Encryption Standard (AES-128) Using UVM

Language: SystemVerilog - Size: 992 KB - Last synced at: 9 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

OmniaMohamed12/S-AES-Design-and-Verification-using-SystemVerilog-and-UVM

Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.

Language: SystemVerilog - Size: 29.3 KB - Last synced at: 9 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

michellavezzo/clock_verilog

First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.

Language: SystemVerilog - Size: 60.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Pritam-Sethuraman/Calc1

Language: Verilog - Size: 39.1 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

reity/article-specifications-for-distinguishing-functions

This article presents a technique for assembling concise, lightweight specifications and unit tests for verifying the identity of a function; the technique sacrifices completeness to enable compact and portable specifications.

Language: Jupyter Notebook - Size: 13.7 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

PSSTools/psde 📦

Provides Eclipse plug-ins for developing Accellera PSS

Language: Rich Text Format - Size: 3.98 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 3