GitHub / Choaib-ELMADI / getting-started-with-systemverilog
Getting started with SystemVerilog: Hardware Description Language for design and verification.
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PURL: pkg:github/Choaib-ELMADI/getting-started-with-systemverilog
Stars: 6
Forks: 1
Open issues: 0
License: None
Language: SystemVerilog
Size: 1.02 MB
Dependencies parsed at: Pending
Created at: 20 days ago
Updated at: 12 days ago
Pushed at: 12 days ago
Last synced at: 12 days ago
Topics: asic, design, fpga, hardware, hardware-designs, hdl, rtl, rtl-design, systemverilog, systemverilog-hdl, testbench, testing, uvm, uvm-verification, verification