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GitHub / tharunchitipolu / RISC-V-32I-based-core-with-Advanced-Extensible-Interface

5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tharunchitipolu%2FRISC-V-32I-based-core-with-Advanced-Extensible-Interface

Stars: 9
Forks: 0
Open issues: 0

License: None
Language: Verilog
Size: 518 KB
Dependencies parsed at: Pending

Created at: almost 3 years ago
Updated at: 5 months ago
Pushed at: 5 months ago
Last synced at: 5 months ago

Topics: arm, axi3, cache, computer-architecture, digitaldesign, pipeline, processor, risc-v, systemverilog, testbench, verilog, verilog-hdl

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