Topic: "digitaldesign"
ahmed-agiza/EDAViewer
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
Language: JavaScript - Size: 3.09 MB - Last synced at: 4 days ago - Pushed at: over 2 years ago - Stars: 71 - Forks: 13

tharunchitipolu/RISC-V-32I-based-core-with-Advanced-Extensible-Interface
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
Language: Verilog - Size: 518 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 9 - Forks: 0

siorpaes/SimpleSoC
Very simple Cortex-M1 SoC design based on ARM DesignStart
Language: C - Size: 206 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 8 - Forks: 2

ahegazy/HDL
This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
Language: Verilog - Size: 209 KB - Last synced at: about 1 year ago - Pushed at: about 5 years ago - Stars: 6 - Forks: 2

Abdelrahman-Adel610/Full_AES-Verilog
Full AES (Verilog)
Language: Verilog - Size: 13.7 MB - Last synced at: 10 months ago - Pushed at: about 1 year ago - Stars: 4 - Forks: 3

GabbedT/FIFO
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
Language: SystemVerilog - Size: 117 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 0

Munees-Sanid/verilog_code_challenge
Verilog Code Challenge – KVLSI Kohort 2
Language: Verilog - Size: 1.16 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 3 - Forks: 0

yezzfusl/FlexComSwitch
VHDL controller for dynamic protocol switching (CAN, LIN, FlexRay).
Language: VHDL - Size: 18.6 KB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0

Pirate-Emperor/CipherX
CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.
Language: Verilog - Size: 2.61 MB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 2 - Forks: 0

GabbedT/Arithmetic-Circuits
This repository contains different modules which execute arithmetic operations.
Language: SystemVerilog - Size: 188 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

abxhr/University
A repo to store the coursework I do in college! 🎓
Language: Java - Size: 24.1 MB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 1

serhaturtis/DD-LTC2311-16
IP Module For LTC2311 ADC
Language: SystemVerilog - Size: 414 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1

mshetty149/Hardware-Designs
RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
Language: Verilog - Size: 4.12 MB - Last synced at: 11 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

mshetty149/Placer-and-router-software-for-VLSI
Placer and Router for standard cells
Language: NewLisp - Size: 566 KB - Last synced at: 11 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

mramyasri777/Vending-Machine
The Vending Machine Controller is a digital IP that manages item dispensing and change handling based on currency input. It supports flexible configuration, high-speed operation at 100 MHz, and efficient stock management through an APB interface.
Language: Verilog - Size: 4.88 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 0 - Forks: 0

SOWJANYA-MADANA/Vending-Machine
A Verilog-based RTL design of a configurable vending machine controller with APB configuration, asynchronous input handling, and real-time item dispensing.
Size: 0 Bytes - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 0 - Forks: 0

Krishnasa1/vending_machine
This project implements a Verilog-based Vending Machine Controller with support for APB configuration, item dispensing, and currency validation. It features FSM control, clock domain synchronization, and is fully synthesizable for FPGA applications.
Size: 0 Bytes - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 0 - Forks: 0

arunbasilpaul/Alarm_Clock
A HDL twist to the traditional Alarm Clock with opportunity to set an alarm and a 7-segment display
Language: VHDL - Size: 61.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

0xIsagiY9/College-4th-FirstTerm
Senior Year - First Term - Faculty of Engineering Helwan University - Repository
Size: 548 MB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Anshuman-02/PWM-Generator-with-Variable-Duty-Cycle
VHDL project for a PWM Generator with variable duty cycle control and testbench simulation.
Language: VHDL - Size: 268 KB - Last synced at: about 2 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Nadhirus/VHDL-Nios-extension
This is a repo for my digital design labwork @Paris-Saclay
Language: VHDL - Size: 1000 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

idznizam/crispy
Digital Electronics Design, Computer Organization Architecture...and all the low level stuff
Language: SCSS - Size: 1.68 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

EswarAdithya011/Mealy-Sequence-Detector-CMOS-90nm
This repository contains the design and implementation of a 4-bit Mealy Machine-based Overlapping Sequence Detector for detecting the sequence "1001" using 90nm CMOS technology and simulated in Cadence Virtuoso. The design employs SISO registers and master-negative edge-triggered D flip-flops within a Mealy machine architecture.
Size: 1.37 MB - Last synced at: 4 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

rhit-bryantlj/VerilogPongGame
Repository containing the code for implementing the classic game Pong on a Nexys A7 Digilent FPGA development board.
Language: SystemVerilog - Size: 6.45 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1

z4chh/FPGA_Slot_Machine
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
Language: SystemVerilog - Size: 12.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Mohamedsalem80/VHDL-tutorial
VHDL tutorial
Language: VHDL - Size: 1.26 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Escaper2/DigitalDesign-Engineer-School
Тестовое задание для DigitalDesign
Language: HTML - Size: 820 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Myriam2002/Digital_lock_for_a_safe
Basic digital lock system for safes, employing logic gates 🔐
Size: 1.72 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

AnuragSChatterjee/NUS-EE2026-Digital-Design
Took a module on Digital Design Fundamentals during my year 2 of my undergraduate studies of Electronic Circuits done using VHDL and Verilog, with a final project on FPGA Programmed Flappy Bird Gaming System using Sound and Light effects.
Size: 350 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

AntEncarnacion/digital-systems-playground 📦
Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.
Language: VHDL - Size: 38.1 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

VladMarianCimpeanu/digital-design-project-
images equalizer in VHDL
Language: TeX - Size: 2.49 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 2

darter-funny/fidget-spinner-republic
For all the fidget spinneteers out there
Size: 37.1 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

Arna-Maity/Verilog_Modules
This repository contains a few useful Verilog modules
Language: Verilog - Size: 62.5 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

ahagmann/dtc
Digital Design Timing Constraints
Language: Jupyter Notebook - Size: 72.3 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

marconip/magazines-presentation-interface
a quick interface to any digital device that features magazines as a product
Language: CSS - Size: 2.53 MB - Last synced at: almost 2 years ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

jacobhuesman/digital_design
Miscellaneous stuff from the NDSU Digital Design Class
Language: Mathematica - Size: 24.4 KB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 0 - Forks: 0
